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A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
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4.7.3. SFP+
The SFP+ Port meets SFF-8431 Industrial Standard. The connector part number is Samtec MECT-110-01-M-D-RA1. The cage part number is Molex 74754-0101. The PCB trace insertion loss is less than -5 dB and return loss less than -10 dB.
SFP+ signals (TX_disable, RS0/1, MOD_ABS, LOS, Fault) are mapped to the dedicated transceiver I/O in Intel® MAX® 10.
Pin Name | Schematic Signal Name | Direction | Description |
---|---|---|---|
PIN_BJ5 | SFPA_TX_N | Output | GXBR4C_TX_CH0N |
PIN_BJ4 | SFPA_TX_P | Output | GXBR4C_TX_CH0P |
PIN_BH10 | SFPA_RX_N | Input | GXBR4C_RX_CH0N |
PIN_BH9 | SFPA_RX_P | Input | GXBR4C_RX_CH0P |
PIN_AT9 | REFCLK_SFPA_P | Input | REFCLK_GXBR4C_CHBP |
PIN_AT10 | REFCLK_SFPA_N | Input | REFCLK_GXBR4C_CHBN |