Visible to Intel only — GUID: tiv1494627546088
Ixiasoft
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
Visible to Intel only — GUID: tiv1494627546088
Ixiasoft
3.2. Default Setup of the Development Kit
This development kit ships with its board switches preconfigured to support the design examples in the kit.
- Power up the development board by using the included power supply.
- When configuration is complete, the configuration done green LED (D22) illuminates, signaling that the Intel® Stratix® 10 device is configured successfully.
CAUTION:
Use only the provided power supply. Power regulation circuits on the board can be damaged by power supplies with greater voltage and a lower-rated power supply may not be able to provide enough power for the board.
Checkpoint | Name | Reference | Description |
---|---|---|---|
1 | Power Switch | SW7 | Power is turn off at left position |
2 | Power Adapter connector | J25, J55 | Both connectors can be used to connect the power adapter |
3 | Intel Intel® Enpirion® | J29 | You can install Intel® Enpirion® dongle to monitor the board power rails. Switch 8 is at off position. |
4 | JTAG Dongle connector | J1 | You can install Intel® JTAG dongle to access FPGA |
5 | JTAG Switch | SW1 | Default Setup from bit 1 to bit 8 is “off, off, on, on, on, on, on, on”: Intel® Stratix® 10 SoC and Intel® MAX® 10 are on the JTAG chain |
6 | USB JTAG Port | J57 | You need connect Micro USB cable to access Intel® Stratix® 10 SoC |
7 | 12V Fan Connector | J16 | You need use it to connect thermal Fan |
8 | Boot Switch | SW4 | Default set up from bit 1 to Bit 4 is “on, off, on, off” FPGA/HPS I2C is enabled. Daughter card power is on |
9 | MSEL Switch | SW2 | Default Setup is “on on on on”: JTAG mode |