Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide

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ID 683175
Date 12/03/2021
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Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices 2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices 3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices 5. Factors Affecting the Accuracy of the Early Power Estimator 6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices x
1.1. Intel® Stratix® 10 EPE Power Model Status 1.2. Definitions of Power Terms Used in this Document
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices 2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator
2.2. Download and Install the Early Power Estimator for Intel® Stratix® 10 Devices x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption with the Intel® Stratix® 10 Early Power Estimator x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface x
3.1. Intel® Stratix® 10 EPE Input Fields 3.2. Intel® Stratix® 10 EPE Output Fields 3.3. Intel® Stratix® 10 EPE Input/Output Fields 3.4. Intel® Stratix® 10 EPE Field Shading 3.5. Intel® Stratix® 10 EPE Input Field Dependencies 3.6. Intel® Stratix® 10 EPE Buttons
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices x
4.1. Intel® Stratix® 10 EPE - Common Worksheet Elements 4.2. Intel® Stratix® 10 EPE - Main Worksheet 4.3. Intel® Stratix® 10 EPE - Logic Worksheet 4.4. Intel® Stratix® 10 EPE - RAM Worksheet 4.5. Intel® Stratix® 10 EPE - DSP Worksheet 4.6. Intel® Stratix® 10 EPE - Clock Worksheet 4.7. Intel® Stratix® 10 EPE - PLL Worksheet 4.8. Intel® Stratix® 10 EPE - I/O Worksheet 4.9. Intel® Stratix® 10 EPE - I/O-IP Worksheet 4.10. Intel® Stratix® 10 EPE - XCVR Worksheet 4.11. Intel® Stratix® 10 EPE - HPS Worksheet 4.12. Intel® Stratix® 10 EPE - HBM Worksheet 4.13. Intel® Stratix® 10 EPE - Thermal Worksheet 4.14. Intel® Stratix® 10 EPE - Report Worksheet 4.15. Intel® Stratix® 10 EPE - Intel® Enpirion® Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator x
5.1. Toggle Rate 5.2. Temperature
1. Overview of the Early Power Estimator for Intel® Stratix® 10 Devices
2. Setting Up the Early Power Estimator for Intel® Stratix® 10 Devices
3. Early Power Estimator for Intel® Stratix® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Stratix® 10 Devices
5. Factors Affecting the Accuracy of the Early Power Estimator
6. Document Revision History for Early Power Estimator for Intel® Stratix® 10 FPGAs User Guide
A. Measuring Static Power

4.10. Intel® Stratix® 10 EPE - XCVR Worksheet

The XCVR worksheet of the Early Power Estimator (EPE) for Intel® Stratix® 10 devices allows you to enter XCVR resources and their settings for all modules in your design. The power of transceiver I/O pins is included in this worksheet. The power of transmitter PLLs for L-tile and H-tile transceivers is not included in this worksheet, but is specified in the PLL worksheet instead.
Figure 18. XCVR Worksheet of the Early Power Estimator

The Early Power Estimator makes the following simplifying assumptions about the transceiver clock network and the blocks used for L-tile and H-tile transceivers:

Table 13.  General Settings in the XCVR Worksheet
Input Parameter Description
Total Thermal Power (W) Total power dissipated in all modules on this page (in Watts). This power excludes the power the L-tile and H-tile transmitter PLLs, whose power is provided in the PLL worksheet.
Treatment of Unused HSSI Dies Specify how L-tile and H-tile HSSI dies not actively used by transceiver channels should be treated when calculating static power. If none of the transceiver channels or PLLs on an HSSI die are used, the die can be powered down or remain powered. The voltage of unused dies that are powered can be selected to minimize static power, or to minimize the number of power supply voltages required.

For example, if active H-tile transceiver channels use VCCR_GXB=1.12V, selecting Minimize Leakage assumes that the unused-but-powered H-tile dies use VCCR_GXB=1.03V, which is the lowest supported voltage, thus minimizing leakage.

Selecting Minimize Number of Supply Voltages assumes that the unused-but-powered banks use VCCR_GXB=1.12V, which is the voltage used by active channels, thus eliminating the need for the 1.03V power supply on VCCR_GXB.

Early Power Estimator uses information in columns XCVR Die ID, Starting Channel Location, and # of Channels on the XCVR worksheet, along with columns # PLL Blocks and XCVR Die ID on the PLL worksheet to determine whether dies are actively used.

This setting does not apply to E-tile transceivers, because E-tile transceiver dies can never be powered down.

Each row in the XCVR worksheet represents a separate transceiver domain. Enter the following parameters for each transceiver domain:

Table 14.  XCVR Worksheet Information
Column Heading Description
Module Specifies a name for the module. This is an optional value.
Tile

Specifies the type of transceiver die on which transceiver channels are located. Some devices may include more than one type of transceiver die.

This field changes depending on the device options that you choose on the Main worksheet.

XCVR Die ID Specify the transceiver die on which transceiver channels on this row are located.
Starting Channel Location Specify the starting location within the bank for the channels specified in this row. For example, if a given row contains 3 channels, and starting location is specified to be 12, channels are assumed to be in locations 12, 13, and 14. Location 0 denotes the bottom-most channel on the transceiver die.
# of Channels

Specifies the number of channels used in this transceiver domain. Each row represents one transceiver domain. These channels are grouped together in one transceiver bank, or two or more adjacent transceiver banks and clocked by one or more common transmitter PLLs.

For E-tile transceivers, when the channel is configured in PAM4 mode and the data rate is greater than 28.9 Gbps, enter two physical channels to represent a single PAM4 logical channel.

Note: For PCI Express protocols with Hard IP, the Hard IP block supports x1, x2, x4, x8, and x16 modes. The total number of channels using PCI Express Hard IP on a single transceiver die must be one of 1, 2, 4, 8, or 16, because each L-tile or H-tile die supports only one PCI Express Hard IP.
Operation Mode

Specifies whether the hardware is configured in full duplex transceiver mode (Receiver and Transmitter) or in Receiver Only or Transmitter Only mode. Allowed values depend on the selected PCS/HIP mode.

Data Rate (Mbps) Specifies the data rate (in Mbps) for the transceiver. Allowed values depend on the selected protocol and selected device. For L-tile and H-tile transceiver dies, allowed values also depend on the VCCR_GXB and VCCT_GXB voltages.
Digital/Analog Interface Width

Specify the width of the parallel data bus between PCS and PMA.

For E-tile PMA Direct, set to PMA parallel data width, even if FPGA FIFO widens the interface. As an example, for 25 Gbps PMA Direct you would typically set this value to 32. When the FEC or EHIP is used, you would set this value to 32 for NRZ mode and 64 for PAM4 mode.

Power Mode

E-tile transceivers can operate at either Normal Power Mode or Low Power Mode.

For the thermal and regulator sizing, you must set the E-tile transceivers in the Normal Power Mode, because your board design must take into consideration the maximum power conditions. Refer to the E-tile Transceiver PHY User Guide for information on how to switch transceivers from Normal Power Mode to Low Power Mode.

FEC Specify the Forward Error Correction setting. This field is applicable only to E-tile transceivers.
EHIP Specify the Ethernet Hard IP protocol. This field is applicable only to E-tile transceivers.
Modulation Mode Specify the data modulation mode of transceiver channels. This field is applicable only to E-tile transceivers.
Digital Frequency (MHz) Specify the digital frequency at which the digital portion of the transceiver (including FEC and EHIP) operates. This field is applicable only to E-tile transceivers.
# Refclks Specify the number of reference clocks in use. If another interface on this tile is using the same reference clock, and you have already entered this clock in another row, enter 0 in this row to avoid double counting. This field is applicable only to E-tile transceivers.
Refclk Frequency Specify the reference clock frequency. This field is applicable only to E-tile transceivers.
Application Specify the application type, which determines values for advanced channel options. Select Custom to enable manual editing of advanced channel options for the current row. This field is applicable only to L-tile and H-tile transceivers.
Protocol Mode

Specifies the mode in which the PCS, HIP, and PCIE blocks operate. This mode depends on the XCVR tile and the communication protocol or standard that the channels on this row implement.

VCCR_GXB and VCCT_GXB Voltage Specifies the voltage of the VCCR_GXB and VCCT_GXB rails. Allowed values depend on the selected device and selected data rate. This field is applicable only to L-tile and H-tile transceivers.
VOD Setting The output differential voltage (VOD) setting of the transmitter channel PMA. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
VOD Voltage The output differential voltage (VOD) of the transmitter channel PMA (in mV). This voltage depends on the VOD setting and the VCCT_GXB voltage. This field is applicable only to L-tile and H-tile transceivers.
Pre-Emphasis Setting–First Pre-Tap Specifies the pre-emphasis setting used by the transmitter channel PMA. Set to Off if the tap value is 0; otherwise, set to On. If pre-emphasis settings are set to On, power consumption does not depend on the magnitude nor the sign (positive or negative) of individual taps. To enable these settings, select Custom in the Application column.
Pre-Emphasis Setting–First Post-Tap
DFE Specify mode of the decision feedback equalizer (DFE). Allowed values depend on the selected data rate. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
Adaptation Specify if the adaptation feature is used. This option should be enabled if the channels use either CTLE adaptation or DFE adaptation. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
Transmitter High-Speed Compensation Specifies if the power distribution network (PDN) induced inter-symbol interference (ISI) compensation is enabled in the TX driver. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
Digital Power (W)

For L-tile and H-tile transceivers, the total power of the transmitter channel PCS, receiver channel PCS, and Embedded Multi-die Interconnect Bridge (EMIB) blocks used by all channels on this row (in W). This power excludes power of PCI Express Hard IP blocks, which may be shared among channels in multiple rows.

For E-tile transceivers, the total power of the Forward Error Correction (FEC), Ethernet Hard IP (EHIP), and Embedded Multi-die Interconnect Bridge (EMIB) blocks used by all channels on this row (in W).

Analog Power (W) The total power of all analog circuitry on this row (in Watts). This power excludes the power of PCS, FEC, EHIP, and Embedded Multi-die Interconnect Bridge (EMIB) blocks, whose power is provided in the Digital Power column, and L-tile and H-tile transmitter PLLs, whose power is provided on the PLL worksheet.

This power also excludes the power of blocks such as PCI Express Hard IP, clock network, and other blocks that may be shared among channels in multiple rows.

User Comments Enter any comments. This is an optional entry.

For more information about the transceiver architecture of the supported device families, refer to the appropriate Transceiver PHY User Guide for Intel® Stratix® 10 devices.

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