DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

ID 683050
Date 2/01/2023
Public

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2.6. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP design example.
Figure 11.  DisplayPort Intel® FPGA IP Design Example Clocking Scheme
Table 14.  Clocking Scheme Signals
Clock Signal Name in Design Description
TX PLL Refclock tx_pll_refclk

135 MHz TX PLL reference clock, that is divisible by the transceiver for all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, and 5.4 Gbps).

Note: The reference clock source of the TX PLL refclock is located at the HSSI refclk pin.
TX Transceiver Clockout gxb_tx_clkout

TX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

Data Rate Symbols per Clock Frequency (MHz)

RBR (1.62 Gbps)

2 (dual)

81
4 (quad) 40.5

HBR (2.7 Gbps)

2 (dual) 135
4 (quad) 67.5

HBR2 (5.4 Gbps)

2 (dual) 270
4 (quad) 135

HBR3 (8.1 Gbps)

4 (quad) 202.5
 
TX PLL Serial Clock gxb_tx_bonding_clocks

Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.

RX Refclock rx_cdr_refclk

135 MHz transceiver clock data recovery (CDR) reference clock, that is divisible by all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps).

Note: The reference clock source of the RX refclock is located at the HSSI refclk pin.
RX Transceiver Clockout gxb_rx_clkout

RX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

Data Rate Symbols per Clock Frequency (MHz)

RBR (1.62 Gbps)

2 (dual)

81
4 (quad) 40.5

HBR (2.7 Gbps)

2 (dual) 135
4 (quad) 67.5

HBR2 (5.4 Gbps)

2 (dual) 270
4 (quad) 135

HBR3 (8.1 Gbps)

4 (quad) 202.5
 
Management Clock rx_rcfg_mgmt_clk

tx_rcfg_mgmt_clk

A free running 100 MHz clock for both Avalon® memory-mapped interface for reconfiguration and PHY reset controller for transceiver reset sequence.

Component Required Frequency (MHz)
Avalon® memory-mapped reconfiguration 100 – 125
Transceiver PHY reset controller 1 – 500
 
Audio Clock dp_audio_clk

DisplayPort audio clock.

16 MHz Clock clk_16

16 MHz clock used to encode and decode auxiliary channel in the DisplayPort Intel® FPGA IP source and sink IP cores. This clock is also used as a reference clock in the Pixel Clock module for fractional calculation.

Calibration Clock dp_rx_clk_cal

dp_tx_clk_cal

A 50 MHz calibration clock input that must be synchronous to the Transceiver Reconfiguration module's clock. This clock is used in the DisplayPort Intel® FPGA IP core's reconfiguration logic.

RX Video Clock dp_rx_vid_clkout

Video clock for DisplayPort sink to clock video data stream.

If MAX_LINK_RATE = HBR2 and PIXELS_PER_CLOCK = Dual, video clock uses 300 MHz. Otherwise, fixed to 160 MHz.

TX Video Clock tx_vid_clk

Recovered video clock from the PCR module that reflects the actual video clock frequency.

Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 0.

TX IM Clock tx_im_clk

Video clock for DisplayPort source to clock video data stream. Must be the same as the RX video clock in this design.

Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 1.