HDMI Stratix® 10 FPGA IP Design Example User Guide

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ID 683701
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives 6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Hardware and Software Requirements 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example x
3.1. HDMI RX-TX Retransmit Design Block Diagram 3.2. Creating TX or RX Only Designs 3.3. Design Components 3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.5. Clocking Scheme 3.6. Interface Signals 3.7. Design RTL Parameters 3.8. Hardware Setup 3.9. Simulation Testbench 3.10. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios® V Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Setting Up the Hardware 4.3.2. Generating the Design 4.3.3. Including HDCP Production Keys 4.3.4. Compiling the Design 4.3.5. Viewing the Results
4.3.3. Including HDCP Production Keys x
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. Viewing the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide

6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version Intel® FPGA IP Version Changes
2024.04.09 24.1 19.7.3
  • Updated mentions of Nios® II to Nios® V (where applicable).
  • Changed the document title from HDMI Intel Stratix 10 FPGA IP Design Example User Guide to HDMI Stratix 10 FPGA IP Design Example User Guide.
  • Added a note about obtaining Nios® V evaluation license in the Generating the Design topic.
2024.01.26 22.4 19.7.1 Removed the note regarding support for Bitec HDMI daughter card revisions 4 and 6 from the Hardware and Software Requirementstopic.
2022.12.27 22.4 19.7.1 Added a new parameter for selecting HDMI daughter card revision to the Hardware and Software Requirements section of the design example quick start guide.
2022.09.07 22.2 19.7.0 Edited Disabling HDR Insertion and Filtering chapter to incorporate steps to disable HDR InfoFrame insertion and filtering for TMDS mode design.
2022.08.02 22.2 19.7.0
  • Notification of removal of Cygwin component from the Windows* version of Nios II EDS and the requirement to install WSL for Windows* users.
  • Updated daughter card version from Revision 4 to 9 where applicable throughout the document.
2021.11.12 21.3 19.6.1
  • Replaced AN556 to Intel Stratix 10 Device Security User Guide in Protection of Encryption Key Embedded in FPGA Design.
  • Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
  • Removed the following figures:
    • Data array of Facsimile Key R1 for RX Private Key
    • Data arrays of HDCP Production Keys (Placeholder)
    • Data array of HDCP Protection Key (Predefined key)
    • HDCP protection key initialized in hdcp2x_tx_kmem.mif
    • HDCP protection key initialized in hdcp1x_rx_kmem.mif
    • HDCP protection key initialized in hdcp1x_tx_kmem.mif
2021.09.15 21.1 19.6.0 Removed references to ncsim
2021.05.12 21.1 19.6.0
  • Added SUPPORT_HDCP_KEY_MANAGE = 1 to the description for Figure 29 HDCP Over HDMI Design Example Block Diagram.
  • Added the steps in HDCP key memory files in Design Walkthrough.
  • Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
  • Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
  • Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
  • Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter and Frequently Asked Questions.
2020.3.29 21.1 19.6.0
  • Updated Figure Components Required for RX-Only or TX-Only Design.
  • Updated Table Generated RTL Files.
  • Updated Figure HDMI RX Top Components.
  • Removed Section HDMI RX Top Link Training Process.
  • Updated the steps in Running the Design in Different FRL Rates.
  • Updated Figure HDMI 2.1 Design Example Clocking Scheme.
  • Updated Table Clocking Scheme Signals.
  • Updated Figure HDMI RX-TX Block Diagram to add a connection from Transceiver Arbiter to TX top.
2020.12.14 20.4 19.6.0
  • Updated the HDMI Intel FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices section with information about the newly added HDMI 2.1 design example with FRL mode.
  • Added a new chapter, Detailed Description for HDMI 2.1 Design Example (Support FRL Enabled) that contains all the relevant information about the newly added design example.
  • Updated the HDCP Over HDMI 2.0 Design Example section:
    • Updated topic title HDCP Over HDMI 2.0 Design Example to HDCP Over HDMI 2.0/2.1 Design Example
    • Added new hardware setup when SUPPORT_FRL = 1 in the Set Up the Hardware section.
    • Edited the Include HDCP Production Keys section to updated the design example top level file to <Intel Quartus Prime project name>.v
    • Edited the Compile the Design section to update the .qpf file to <projectdirectory /quartus/<Intel Quartus Prime project name>.qpf
    • Updated table name Push Button and LED Indicators to Push Button and LED Indicators (SUPPORT_FRL = 0).
    • Added a new Table: Push Button and LED Indicators (SUPPORT_FRL =1).
2020.09.28 20.3 19.5.0
  • Updated the directory structure for Stratix® 10 design example and the generated files list in the Directory Structure section.
  • Updated the block diagrams in the HDMI 2.0 RX-TX Retransmit Design Block Diagram, Generating TX or RX Only Designs, and Clocking Scheme sections.
  • Updated the description for the RX and TX core components and removed the description for the PIO and I2C Master (TX) components from the Design Components section.
  • Updated the description for the transceiver clock signals in the Clocking Scheme section.
  • Added RX CDR reference clock information in the Clocking Scheme section.
  • Removed irrelevant signals, and added or edited the description of the following HDMI design example signals in the Interface Signals section:
    • clk_fpga_b3_p
    • user_led_r
    • fmcb_la_tx_p_11
    • fmcb_la_rx_n_9
    • fr_clk
    • ls_clk_out
    • sys_init
    • clock_bridge_0_in_clk_clk
    • rx_pma* signals
    • rx_rcfg_en_export
    • rx_rst_xcvr_export
    • tx_rcfg_en_pio_external_connection_export
    • tx_iopll__rcfg_mgmt_translator_avalon_anti_slave_waitrequest
  • Added the EDID_RAM_ADDR_WIDTH parameter in the Design RTL Parameters section.
  • Added a note that the simulation testbench is not supported for designs with the Include I2C parameter enabled and updated the simulation message in the Simulation Testbench section.
  • Updated the Upgrading Your Design section.
2020.06.22 20.2 19.4.0
  • Added the build_sw_hdcp.sh script and removed the runall.tcl script from the Directory Structure section. The runall.tcl script is applicable only for the Quartus® Prime Standard Edition software.
  • Added a list of HDMI Intel® FPGA IP design examples offered for Stratix® 10 devices in the HDMI Intel® FPGA IP Design Example Quick Start Guide section.
  • Added a new section about the HDCP design example: HDCP Over HDMI 2.0 Design Examples. The HDCP feature is now available for Stratix® 10 devices.
2019.05.24 19.1 19.1
  • Updated the Directory Structure section to remove information about the i2c_master folder and the related files; and added the following files:
    • tx_control_src/intel_fpga_i2c.h
    • tx_control_src/intel_fpga_i2c.c
  • Updated the Generating the Design section to change the part number for the Stratix® 10 device to 1SG280LU2F50E2V and 1SG280HU2F50E2VG. The design example targets the Stratix® 10 production device now.
  • Edited the Hardware and Software Requirements section to include Stratix® 10 L-tile and update the Bitec HDMI FMC 2.0 daughter card to revision 11.
  • Updated the HDMI Intel® FPGA IP Design Example Parameters section to include new options for the Select Board parameter. You can choose to use either the Stratix 10 GX FPGA H-tile or L-tile development kit for your Stratix® 10 designs.
  • Added the following I2C and Hot Plug Detect signals in the Interface Signals section:
    • nios_tx_i2c_sda_in
    • nios_tx_i2c_scl_in
    • nios_tx_i2c_sda_oe
    • nios_tx_i2c_scl_oe
    • nios_ti_i2c_sda_in
    • nios_ti_i2c_scl_in
    • nios_ti_i2c_sda_oe
    • nios_ti_i2c_scl_oe
    • hdmi_ti_i2c_sda
    • hdmi_ti_i2c_sda
  • Removed the following I2C and Hot Plug Detect signals in the Interface Signals section:
    • tx_i2c_avalon_waitrequest
    • tx_i2c_avalon_address
    • tx_i2c_avalon_writedata
    • tx_i2c_avalon_readdata
    • tx_i2c_avalon_chipselect
    • tx_i2c_avalon_write
    • tx_i2c_avalon_irq
  • Added the following Platform Designer signals in the Interface Signals section:
    • reset_bridge_0_in_reset_reset_n
    • i2c_master_i2c_serial_sda_in
    • i2c_master_i2c_serial_scl_in
    • i2c_master_i2c_serial_sda_oe
    • i2c_master_i2c_serial_scl_oe
    • i2c_master_ti_i2c_serial_sda_in
    • i2c_master_ti_i2c_serial_scl_in
    • i2c_master_ti_i2c_serial_sda_oe
    • i2c_master_ti_i2c_serial_scl_oe
  • Removed the following Platform Designer signals in the Interface Signals section:
    • cpu_clk_reset_n
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest
    • oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect
  • Updated the description for fmcb_dp_m2c_p and fmcb_dp_c2m_p signals to add transceiver serial data mapping to the HDMI channels.
  • Updated the Design RTL Parameters section to add information that the default Bitec HDMI FMC 2.0 daughter card is revision 11.
  • Added Upgrading Your Design section to provide guidelines about upgrading your existing design to the latest version.
2018.05.07 18.0 18.0 Initial release.
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