Visible to Intel only — GUID: wfk1475274505364
Ixiasoft
Overview of HPS Modules
HPS MPU Subsystem Differences
Stratix 10 HPS Interface to SDM
Booting and Configuration Differences
HPS Cache Coherency Controller Differences
HPS System Memory Management Differences
HPS On-Chip RAM Differences
HPS Error Correction Differences
HPS DMA Controller Differences
HPS Clock Manager Differences
HPS Reset Manager Differences
HPS FPGA Manager Differences
HPS System Manager Differences
HPS Scan Manager Differences
HPS Security Feature Differences
HPS Interconnect Differences
HPS-FPGA Bridge Differences
HPS General Purpose I/O Interface Differences
HPS I/O Configuration Differences
HPS SDRAM Controller Subsystem Differences
HPS NAND Flash Controller Differences
HPS SD/MMC Controller Differences
HPS Quad SPI Flash Controller Differences
HPS USB 2.0 OTG Controller Differences
HPS EMAC Differences
HPS SPI Controller Differences
HPS I2C Controller Differences
HPS UART Controller Differences
HPS CAN Controller Differences
HPS Timer Differences
HPS Watchdog Timer Differences
HPS CoreSight Debug and Trace Differences
Document Revision History
Visible to Intel only — GUID: wfk1475274505364
Ixiasoft
Stratix 10 HPS Interface to SDM
| Secure Device Feature | Cyclone V SoC | Arria V SoC | Arria 10 SoC | Stratix 10 SoC |
|---|---|---|---|---|
| Secure device manager implemented | No | No | No | Yes |
The SDM is a hard subsystem in the FPGA portion of the Stratix 10 device that is responsible for:
- Configuring the FPGA
- Bootstrapping the HPS
- Providing device-wide security features
The SDM is responsible for copying the HPS bootloader6 from its flash storage device to the on-chip RAM inside the HPS. Since the SDM is also used for configuration, the HPS can request that the SDM configure or reconfigure the FPGA. The SDM and HPS communicate with one another through the SDM interface, which is a bridge that exposes the address map of each subsystem to the other.
6 typically U-Boot or Unified Extensible Firmware Interface (UEFI)