AN 797: Partially Reconfiguring a Design: on Intel® Arria® 10 GX FPGA Development Board

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ID 683497
Date 12/11/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board

Step 4: Adding the Partial Reconfiguration Controller IP

The Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP interfaces with the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block to manage the bitstream source.
Follow these steps to add the IP core to your Intel® Quartus® Prime project:
  1. Type Partial Reconfiguration in the IP Catalog (Tools > IP Catalog).
  2. Double-click Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
  3. In the Create IP Variant dialog box, type pr_ip as the File Name, and then click Create. The parameter editor appears.
  4. Turn on Use as partial reconfiguration internal host, Enable JTAG debug mode, and Enable freeze interface. Turn off Enable Avalon-MM slave interface. Select 16 bits for the Input data width.
    Figure 7. Partial Reconfiguration Controller IP Core Parameters
  5. Click File > Save, and exit the parameter editor without generating the system. The parameter editor generates the pr_ip.ip IP variation file and adds the file to the blinking_led project.
    Note:
    1. If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the following line:
      set_global_assignment -name IP_FILE pr_ip.ip
    2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration Controller IP core.
      Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files that you use to create these clocks in the .qsf file for your Intel® Quartus® Prime project revision. For more information, refer to the "Partial Reconfiguration IP Solutions User Guide" chapter of Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.
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