NCO IP Core: User Guide

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ID 683406
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the NCO IP Core 2. NCO IP Core Getting Started 3. NCO IP Core Functional Description A. NCO IP Core User Guide Document Archives 4. Document Revision History
1. About the NCO IP Core x
1.1. Intel® DSP IP Core Features 1.2. NCO IP Core Features 1.3. DSP IP Core Device Family Support 1.4. NCO IP Core MegaCore Verification 1.5. NCO IP Core Release Information 1.6. NCO IP Core Performance and Resource Utilization
2. NCO IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. NCO IP Core Functional Description x
3.1. NCO IP Core Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Core Parameters 3.8. NCO IP Core Interfaces and Signals
3.1. NCO IP Core Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Core Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Core Interfaces and Signals x
3.8.1. Avalon-ST Interfaces in DSP IP Cores 3.8.2. NCO IP Core Signals 3.8.3. NCO IP Core Timing Diagrams
1. About the NCO IP Core
2. NCO IP Core Getting Started
3. NCO IP Core Functional Description
A. NCO IP Core User Guide Document Archives
4. Document Revision History

4. Document Revision History

NCO IP User Guide revision history
Date Version Changes Made
November 2017 2017.11.06
  • Deleted reference to MATLAB testbench support
  • Removed design example
  • Added support for Intel® Cyclone® 10 devices
  • Changed small ROM architecture description.
  • Corrected "deviation of output values" table position 2.
2014.12.15 14.1
  • Added full support for Arria 10 and MAX 10 devices
  • Reordered parameters tables to match wizard
August 2014 14.0 Arria 10 Edition
  • Added support for Arria 10 devices.
  • Added new in_data and out_data bus descriptions.
  • Added Arria 10 generated files description.
  • Removed table with generated file descriptions.
June 2014 14.0
  • Removed device support for Cyclone III and Stratix III devices
  • Added support for MAX 10 FPGAs.
  • Added instructions for using IP Catalog
November 2013 13.1
  • Removed support for the following devices:
    • Arria
    • Cyclone I
    • IHardCopy II, HardCopy III, and HardCopy IV
    • Stratix, Stratix II, Stratix GX, and Stratix II GX
  • Added full support for the following devices:
    • Arria V
    • Stratix V
November 2012 12.1 Added support for Arria V GZ devices.
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