NCO IP Core: User Guide

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ID 683406
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the NCO IP Core 2. NCO IP Core Getting Started 3. NCO IP Core Functional Description A. NCO IP Core User Guide Document Archives 4. Document Revision History
1. About the NCO IP Core x
1.1. Intel® DSP IP Core Features 1.2. NCO IP Core Features 1.3. DSP IP Core Device Family Support 1.4. NCO IP Core MegaCore Verification 1.5. NCO IP Core Release Information 1.6. NCO IP Core Performance and Resource Utilization
2. NCO IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. NCO IP Core Functional Description x
3.1. NCO IP Core Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Core Parameters 3.8. NCO IP Core Interfaces and Signals
3.1. NCO IP Core Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Core Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Core Interfaces and Signals x
3.8.1. Avalon-ST Interfaces in DSP IP Cores 3.8.2. NCO IP Core Signals 3.8.3. NCO IP Core Timing Diagrams
1. About the NCO IP Core
2. NCO IP Core Getting Started
3. NCO IP Core Functional Description
A. NCO IP Core User Guide Document Archives
4. Document Revision History

3.7.1. Architecture Parameters

Table 8.  Architecture Parameters
Parameter Value Description
Generation Algorithm Small ROM, Large ROM, CORDIC, Multiplier-Based Select the required algorithm.
Outputs Dual Output, Single Output Select whether to use a dual or single output.
Device Family Target — Displays the target device family. The target device family is preselected by the value specified in the Quartus II or DSP Builder software. The HDL that is generated for your variation may be incorrect if you change the device family target in this wizard.
Number of Channels 1–8 Select the number of channels when you want to implement a multichannel NCO.
Number of Bands 1–16 Select a number of bands greater than 1 to enable frequency hopping. Frequency hopping is not supported in the serial CORDIC architecture.
Use dedicated multipliers On or off When the multiplier-based algorithm is selected on the Parameters page, turn on to use dedicated multipliers and select the number of clock cycles per output, otherwise the design uses logic elements. This option is not available if you target the Cyclone device family.
CORDIC Implementation Parallel, Serial When you select the CORDIC generation algorithm, you can select a parallel (one output per clock cycle) or serial (one output per 18 clock cycles) implementation.
Clock Cycles Per Output 1, 2. When the multiplier-based algorithm is selected on the Parameters page, you can select 1 or 2 clock cycles per output.
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