Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

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ID 683354
Date 11/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices 4. Interface Signals Description 5. Configuration Registers Description 6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Testing the Design in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking and Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Cases
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case
3.5. Hardware Testing x
3.5.1. Test Procedure
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices
4. Interface Signals Description
5. Configuration Registers Description
6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.11.30 19.1 19.1
  • Updated Figure: Clocking and Reset Scheme for 10GBASE-R Design Example
  • Updated for latest branding standards.
2019.05.10 19.1 19.1
  • Updated all references to Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Updated Table: Parameters in the Example Design Tab:
    • Updated the parameter name Example Design Files for Simulation or Synthesis to Example Design Files.
    • Updated the parameter name Enable NPDME support to Enable Native PHY Debug Master Endpoint (NPDME).
  • Updated Figure: Example Design Tab.
2018.10.03 18.1 18.1
  • Added 10M/100M/1G/2.5G/10G USXGMII Ethernet Design Example for Intel Cyclone 10 GX Devices chapter.
  • Updated the Quick Start Guide chapter:
    • Updated Hardware and Software Requirements topic.
    • Updated Figures: Example Design Tab and Block Diagram of the Hardware Setup.
    • Updated Table: Parameters in the Example Design Tab to include a note to parameter Enable ADME support to clarify that this option is only available from Intel Quartus Prime Pro Edition version 17.1 onwards.
  • Updated the 10GBASE-R Ethernet Design Example for Intel Cyclone 10 GX Devices chapter:
    • Updated the hardware testing description for the Hardware and Software Requirements topic.
    • Updated Figure: Clocking and Reset Scheme for 10GBASE-R Design Example.
    • Updated Table: Hardware Test Cases to update the description of the source gen_conf.tcl command for FMC loopback test case.
  • Updated the Interface Signals Description chapter:
    • Updated Table: Avalon-MM Interface Signals:
      • Added the following signals: csr_mch_write, csr_mch_writedata, csr_mch_read, csr_mch_readdata, csr_mch_address, and csr_mch_waitrequest.
      • Removed the following signals: csr_write, csr_writedata, csr_read, csr_readdata, csr_address, and csr_waitrequest.
  • Updated the Configuration Registers Description chapter:
    • Added the following topics:
      • Register Access Definition
      • 1G/2.5G/5G/10G Multi-rate PHY
    • Removed the Register Map topic.
2018.06.28 18.0 18.0
  • Renamed the document as Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User Guide.
  • Made minor editorial updates to the document.
2018.05.16 18.0 18.0 Initial release.
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