Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes

Download PDF
ID 683328
Date 4/17/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes 2. Issues Addressed in Update 1 3. Issues Addressed in Update 2 4. Software Issues Resolved 5. Software Patches Included in Update Releases 6. Known Issues and Workarounds A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes
2. Issues Addressed in Update 1 x
2.1. Intel® Quartus® Prime Pro Edition Software 2.2. Intel® Quartus® Prime Standard Edition Software 2.3. IP and IP Cores 2.4. DSP Builder for Intel® FPGAs 2.5. Intel High Level Synthesis Compiler 2.6. Intel FPGA SDK for OpenCL*
3. Issues Addressed in Update 2 x
3.1. Intel® Quartus® Prime Pro Edition Software 3.2. IP and IP Cores 3.3. Intel FPGA SDK for OpenCL
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes
2. Issues Addressed in Update 1
3. Issues Addressed in Update 2
4. Software Issues Resolved
5. Software Patches Included in Update Releases
6. Known Issues and Workarounds
A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes

2.2. Intel® Quartus® Prime Standard Edition Software

Intel® Quartus® Prime Software

  • Intel® Quartus® Prime Standard Edition Software Version 18.1 Update 1 has been updated with Curl 7.64.0, CygWin 3.0.3, flexnet_publisher 11.16.1.0, openssl 1.0.2r, python 3.6.8, ccl_sqlite3 3.27.0, sqlite3 (python) 3.26.0, xerces-c++ 3.2.2, and zlib 1.2.11, which include functional and security updates. Update to the latest version of Intel Quartus Prime Design Software as soon as possible.
  • Added Generic Flash Programmer tool, which supports a wide range of third-party QSPI flash devices.

Intel® Quartus® Prime Software GUI

  • In the IP Catalog, the following IP core names were changed:
    • FIR II Intel FPGA IP (was FIR II)
    • FP_ACC_CUSTOM Intel FPGA IP (was ALTERA_FP_ACC_CUSTOM)
    • FP_FUNCTIONS Intel FPGA IP (was ALTERA_FP_FUNCTIONS)

    Also, other IP cores might be renamed to remove "Altera" from their name in the IP Catalog.

  • Added a link to the Intel® Quartus® Prime License Agreements to the About Quartus Prime dialog box.
  • For Cyclone® IV and Intel® Cyclone® 10 LP device families, removed 2.5 V as a valid device I/O voltage.

Intel® Quartus® Prime Command Line

  • Added a link to the Intel® Quartus® Prime License Agreements to the command-line banner.

Intel® Quartus® Prime Device Support

  • For Cyclone® IV and Cyclone® V devices, updated the Serial Flash Loader (SFL) factory image to allow the devices to be programmed with a JTAG indirect configuration file (.jic).

Intel® Quartus® Prime Compilation and Design Flows

  • Updated synthesis to ensure that a non-dedicated reference clock signal (refclk) generates an error message.
  • Fixed an issue causing abnormally large memory size when inferring ROM with read enabled.
  • Fixed an issue that resulted in the following error message:
    Internal Error: Sub-system: AMM, 
File: /quartus/db/amm/amm_atom_mod_util_impl.cpp, Line: 4729

Advanced Link Analyzer (formerly JNEye)

  • Enhanced Advanced Link Analyzer:
    • Added full end-to-end mixed-mode simulation support.
    • Enhanced Channel Viewer to show effective return loss (ERL).
    • Enhanced Channel Designer to add support for both far-end (FEXT) and near-end (NEXT) crosstalk extractions.

Platform Designer (former Qsys)

  • Fixed an issue that prevented simulation of systems using a Intel® Quartus® Prime Standard Edition design.

Programmer

  • Fixed issues that caused programming failures when using Macronix MX25L and Cypress S25FL flash memory devices.
  • Fixed issues that caused programming failures when using Intel EPCQ-A serial configuration devices.

Timing Analyzer

  • Fixed an issue that resulted in the following error message:
    Internal Error: Sub-system: STA, 
File: /quartus/tsm/sta/sta_report_metastability.cpp, Line: 2264
Level Two Title