Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes

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ID 683328
Date 4/17/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes 2. Issues Addressed in Update 1 3. Issues Addressed in Update 2 4. Software Issues Resolved 5. Software Patches Included in Update Releases 6. Known Issues and Workarounds A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes
2. Issues Addressed in Update 1 x
2.1. Intel® Quartus® Prime Pro Edition Software 2.2. Intel® Quartus® Prime Standard Edition Software 2.3. IP and IP Cores 2.4. DSP Builder for Intel® FPGAs 2.5. Intel High Level Synthesis Compiler 2.6. Intel FPGA SDK for OpenCL*
3. Issues Addressed in Update 2 x
3.1. Intel® Quartus® Prime Pro Edition Software 3.2. IP and IP Cores 3.3. Intel FPGA SDK for OpenCL
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes
2. Issues Addressed in Update 1
3. Issues Addressed in Update 2
4. Software Issues Resolved
5. Software Patches Included in Update Releases
6. Known Issues and Workarounds
A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes

3.2. IP and IP Cores

Unless stated otherwise, the following IP and IP core issues apply to only to Intel® Quartus® Prime Pro Edition software.

Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express IP Core

  • For Intel® Stratix® 10 H-tile devices, fixed an IP generation issue when an enabled Physical Function (PF) has no Virtual Functions (VFs).

Serial Digital Interface (SDI) II Intel® FPGA IP Core

  • For Intel® Stratix® 10 H-tile devices, updated the design examples.
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