Visible to Intel only — GUID: ecr1468819978397
Ixiasoft
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide
1.2. Design Example Detailed Description
1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
Visible to Intel only — GUID: ecr1468819978397
Ixiasoft
1.2.7. Simulation
Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.
Simulators | Simulation Directory | Run Script |
---|---|---|
Riviera-PRO* | /testbench/aldec/ | run_tb_top.tcl |
ModelSim* | /testbench/mentor/ | run_tb_top.tcl |
QuestaSim* | ||
VCS* | /testbench/synopsys/vcs/ | run_tb_top.sh |
VCS* MX | /testbench/synopsys/vcsmx/ | run_tb_top.sh |
Xcelium* | /testbench/xcelium/ | run_tb_top.sh |
The design generates the simulation results which include the transcript or log files in the relevant simulation directory.