Visible to Intel only — GUID: iak1635173823511
Ixiasoft
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide
1.2. Design Example Detailed Description
1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
Visible to Intel only — GUID: iak1635173823511
Ixiasoft
1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
For the latest and previous versions of this user guide, refer to JESD204B Intel Cyclone 10 GX FPGA IP Design Example User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.