Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

5.11. Transaction Layer Configuration Space Signals

Table 35.  Configuration Space Signals These signals are not available if Configuration Space Bypass mode is enabled.

Signal

Direction

Description

tl_cfg_add[3:0]

Output

Address of the register that has been updated. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl.The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl.

The index increments every 8 coreclkout_hip cycles

tl_cfg_ctl[31:0]

Output

The tl_cfg_ctl signal is multiplexed and contains the contents of the Configuration Space registers. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl.

tl_cfg_sts[52:0]

Output

Configuration status bits. This information updates every coreclkout_hip cycle. The following table provides detailed descriptions of the status bits.

hpg_ctrler[4:0]

Input

The hpg_ctrler signals are only available in Root Port mode and when the Slot capability register is enabled. Refer to the Slot register and Slot capability register parameters in Table 6–9 on page 6–10. For Endpoint variations the hpg_ctrler input should be hardwired to 0s. The bits have the following meanings:

Input

  • [0]: Attention button pressed. This signal should be asserted when the attention button is pressed. If no attention button exists for the slot, this bit should be hardwired to 0, and the Attention Button Present bit (bit[0]) in the Slot capability register parameter is set to 0.

Input

  • [1]: Presence detect. This signal should be asserted when a presence detect circuit detects a presence detect change in the slot.

Input

  • [2]: Manually-operated retention latch (MRL) sensor changed. This signal should be asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor does not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor Present bit (bit[2]) in the Slot capability register parameter is set to 0.

Input

  • [3]: Power fault detected. This signal should be asserted when the power controller detects a power fault for this slot. If this slot has no power controller, this bit should be hardwired to 0, and the Power Controller Present bit (bit[1]) in the Slot capability register parameter is set to 0.

Input

  • [4]: Power controller status. This signal is used to set the command completed bit of the Slot Status register. Power controller status is equal to the power controller control signal. If this slot has no power controller, this bit should be hardwired to 0 and the Power Controller Present bit (bit[1]) in the Slot capability register is set to 0.
Table 36.  Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts

Configuration Space Register

Description

[52:49]

Device Status Register[3:0]

Records the following errors:

  • Bit 3: unsupported request detected
  • Bit 2: fatal error detected
  • Bit 1: non-fatal error detected
  • Bit 0: correctable error detected

[48]

Slot Status Register[8]

Data Link Layer state changed

[47]

Slot Status Register[4]

Command completed. (The hot plug controller completed a command.)

[46:31]

Link Status Register[15:0]

Records the following link status information:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active - This bit is only available for Root Ports. It is always 0 for Endpoints.
  • Bit 12: Slot clock configuration
  • Bit 11: Link Training
  • Bit 10: Undefined
  • Bits[9:4]: Negotiated Link Width
  • Bits[3:0] Link Speed

[30]

Link Status 2 Register[0]

Current de-emphasis level.

[29:25]

Status Register[15:11]

Records the following 5 primary command status errors:

  • Bit 15: detected parity error
  • Bit 14: signaled system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[24]

Secondary Status Register[8]

Master data parity error

[23:6]

Root Status Register[17:0]

Records the following PME status information:

  • Bit 17: PME pending
  • Bit 16: PME status
  • Bits[15:0]: PME request ID[15:0]

[5:1]

Secondary Status Register[15:11]

Records the following 5 secondary command status errors:

  • Bit 15: detected parity error
  • Bit 14: received system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[0]

Secondary Status Register[8]

Master Data Parity Error