Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

3.3.2. Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a configuration write to Function 0 starting at time 61859 ns in the simulation.

The timing diagram illustrates the following sequence of events:

  1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Configuration Write, asserting its RxStSop_i and RxStValid_i signals.
  2. At the falling edge of RxStSop_i, the Avalon-MM master interface asserts cfg_wren_o and specifies the data on cfg_wrdata_o[31:0]. The Master interface also assert cfg_writeresponserequest_o, to request completion status from Function 0.
  3. On the falling edge of cfg_writeresponserequest_o, Function 0 asserts cfg_writeresponsevalid_i.
  4. On the falling edge of cfg_writeresponsevalid_i, the TX interface asserts TxStSop_o and TxStValid_o and drives the completion data on TxStData_o[255:0].
Figure 13. Configuration Write to Function 0