Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

5.8. Configuration Space Bypass Mode Interface Signals

In Configuration Space Bypass mode, the soft Configuration Space exchanges control and status information with the Arria® V GZ Hard IP for PCI Express’s Transaction, Data Link and PHY Layers.

Table 31.  Configuration Space Bypass Mode Input Signals Input signals are driven from the Application Layer’s soft Configuration Space to the Transaction Layer’s hard Configuration Space. All signals are synchronous to pld_clk.

Signal Name

Direction

Description

link2csr[12:0]

Input

Bits[12:0] of the link2csr register from the soft Configuration Space.

comclk_reg

Input

Common clock configuration bit of the Link Control register in the soft Configuration Space.

extsy_reg

Input

Extended synchronization bit of the Link Control register in the soft Configuration Space.

max_pload[2:0]

Input

MAX_PAYLOAD_SIZE field of the Device Control register in the soft Configuration Space.

tx_ecrcgen

Input

ECRC Generation Enable which is bit 6 of the Advanced Error Capabilities and Control register (0x18) in the soft Configuration Space.

rx_ecrchk

Input

ECRC Check Enable which is Bit 8 of the Advanced Error Capabilities and Control register (0x18) in the soft Configuration Space.

secbus[7]

Input

MSB of the Secondary Bus Number register in the soft Configuration Space.

secbus[6:0]

Input

Low-order 7 bits of Secondary Bus Number register in the soft Configuration Space.

linkcsr_bit0

Input

Active State Power Management(ASPM)Control which is Bit 0 of the Link Control register in the soft Configuration Space. ASPM is not supported.

tx_req_pm

Input

Assert this signal to request that the TX Data Link Layer send a Power Management Data Link Layer Packet of type tx_typ_pm_pld. Deasserts when tx_ack_pm_pld is asserted.

tx_typ_pm[2:0]

Input

Lowest 3 bits of the type field for the Power Management Data Link Layer Packet being requested by tx_req_pm_pld.

req_phypm[3:0]

Input

Directs the LTSSM to low power mode.

  • req_phypm[3]: L2 request
  • req_phypm[2]: L1 request
  • req_phypm[1]: L0s request
  • req_phypm[0]: exit any low power state to L0
req_phycfg[3:0]

Input

Configuration Space transition request bus:

  • req_phycfg[3]: Link retrain request. Retrain the link by writing 1b’1 in the retrain link bit in the Link Control register.
  • req_phycfg[2]: Recovery link request. Directs the LTSSM to the Recovery state.
  • req_phycfg[1]: Hot Reset request. Directs the LTSSM to the Hot Reset state.
  • req_phycfg[0]: Disable Link request. Directs the LTSSM to the Disable state.
vc0_tcmap_pld[7:1]

Input

Each bit corresponds to a Traffic Class. Bits[7:1] correspond to Traffic Class 7–Traffic Class 1. When a bit is set to 1, indicates that the corresponding Traffic Class maps to VC0. Traffic Class 0 always maps to Virtual Channel 0.

inh_dllp

Input

When asserted, all TLP and DLLP transmission requests are stalled at the TX Data Link to PHY interface, except for NAK and Power Management DLLPs.

inh_tx_tlp

Input

When asserted, all TLP transmission requests are stalled at the TX Transaction Layer to Data Link Layer interface. The Application Layer should assert this signal when requesting a low‑power state.

req_wake

Input

When asserted, requests the LTSSM to exit from a low‑power state.

link3_ctl[1]

Input

Link Control 3 register bit[1]: Link Equalization Request Interrupt Enable. When set to 1, enables the generation of an interrupt to indicate that the Link Equalization Request bit has been set.

link3_ctl[0]

Input

Link Control 3 register bit [0]. Perform Equalization. When set to 1, the downstream port must perform equalization.

Table 32.  Configuration Space Bypass Mode Output Signals Configuration Space Bypass signals that are driven from the hard Configuration Space in the Transaction Layer to the soft Configuration Space implemented in the Application Layer. The Configuration Space Bypass output signals have the prefix bypass_out_cfgbp_. All signals are synchronous to pld_clk.

Signal Name

Direction

Description

lane_err[7:0]

Output

When a bit is set to 1, indicates a lane error that is reported in the Lane Error Status register of the Secondary PCI Express Extended Capability structure. Bit 0 corresponds to lane 0.

link_equiz_req

Output

Reported as Bit 5 in the Link Status 2 register.

equiz_complete

Output

Reported as Bit 1 in the Link Status 2 register.

phase_3_successful

Output

Reported as Bit 4 in the Link Status 2 register.

phase_2_successful

Output

Reported as Bit 3 in the Link Status 2 register.

phase_1_successful

Output

Reported as Bit 2 in the Link Status 2 register.

current_deemph

Output

Current de-emphasis setting reported in the Link Status 2 register.

current_speed[1:0]

Output

Current link speed as reported in the Link Status register. The following encodings are defined:

  • 2'b01: Gen1
  • 2'b10: Gen2
  • 2'b11: Gen3
link_up

Output

When asserted indicates that the link is up and has exited the Configuration.Idle state.

link_train

Output

Reported as Bit 10 of the Link Status register. When asserted, indicates that the link is training.

l0state

Output

When asserted, indicates that the LTSSM is in the L0 state.

l0sstate

Output

When asserted, indicates that the LTSSM is in L0 or L0s state.

rx_val_pm[0]

Output

When asserted, indicates the Configuration Space has received a Power Management DLLP.

rx_typ_pm[2:0]

Output

Signals the type of received PM DLLP. Has the following values:

  • 000b: PM_Enter_L1
  • 001b: PM_Enter_L2L3
  • 011b: PM_AS_Request_L1
  • 100b: PM_Request_Ack
tx_ack_pm

Output

Pulse. Ack from TX Data Link in response to Power Management DLLP request tx_req_pm_pld.

ack_phypm[1:0]

Output

Acknowledge of transition to and from the low-power state when operations have been completed. The acknowledge bit mapping is the same as the request bit mapping.

  • Bit 0: rxelecidle deasserted or Training Sequence 1 (TS1) received, or rxvalid deasserted. Used for L1 exit.
  • Bit 1: RX Electrical Idle Ordered Set detected or TS1 received.
vc_status[0]

Output

When asserted, indicates that VC0 credits are initialized. When asserted, the VC Negotiation Pending bit of the VC Resource Status register can be cleared indicating that negotiation is complete.

rxfc_max

Output

When asserted, indicates the Transaction Layer has no high priority FC updates to send. High priority updates occur under the following conditions:

  1. The FC update timer expires because no new credits have become available in the timeout period since last update.
  2. The source has used all header credits from the last FC update and header credits have freed up.
  3. The last FC update did not give the source enough data credits to send a maximum payload TLP and data credits have since freed up.

Detects when TLP processing is complete for entry into low power state.

txfc_max

Output

When asserted, indicates that Transaction Layer has enough credits to send maximum payload TLPs of all types. Used for entry into low power state.

txbuf_emp

Output

When asserted, indicates there are no Application Layer TLPs pending for transmission in the Transaction Layer.

rpbuf_emp

Output

When asserted, indicates the replay buffer contains no TLPs.

dll_req

Output

When asserted, indicates that the Data Link Layer TX path has a pending request. Used to enable L0s entry or other low-power state. This is a level sensitive signal.

link_auto_bdw_status

Output

When asserted, indicates that the LTSSM detected an autonomous bandwidth change which is reported in the Link Status register.

link_bdw_mng_status

Output

When asserted, indicates that the LTSSM detected a non‑autonomous bandwidth change. Reported in the Link Status register.

rst_tx_margin_field

Output

When asserted, indicates that the Application Layer should reset the Transmit Margin field of the Link Control 2 register in the Application Layer’s soft Configuration Space.

rst_enter_comp_bit

Output

When asserted, indicates that the Application Layer should reset the Enter Compliance bit in the Link Control 2 register in the Application Layer’s soft Configuration Space.

rx_st_ecrcerr[3:0]

Output

Indicates which quad word on rx_st_data contains a TLP with an ECRC error. Only asserted during the cycle that in which the start of packet is asserted. Only valid only if internal ECRC error checking is enabled.

err_uncorr_internal

Output

When asserted, indicates an uncorrectable internal error was detected. This is a real‑time active high pulse.

err_corr_internal

Output

When asserted, indicates a corrected internal error (ECC) detected. This is a real‑time active high pulse.

err_tlrcvovf

Output

When asserted, indicates a receiver overflow error. This is a real‑time active high pulse.

txfc_err

Output

When asserted, indicates a TX Flow Control Protocol error. This is a real‑time active high pulse.

err_tlmalf

Output

When asserted, indicates a malformed TLP was detected and dropped. This is a real‑time active high pulse.

err_surpdwn_dll

Output

When asserted, indicates a surprise down error occurred. This is a real‑time active high pulse.

err_dllrcv

Output

When asserted, indicates a Data Link Protocol Error. This is a real‑time active high pulse.

err_dll_repnum

Output

When asserted, indicates a Replay_NUM rollover. This is a real‑time active high pulse.

err_dllreptim

Output

When asserted, indicates a Replay Timer Timeout. This is a real‑time active high pulse.

err_dllp_baddllp

Output

When asserted, indicates a bad DLLP was detected. This is a real‑time active high pulse.

err_dll_badtlp

Output

When asserted, indicates a bad TLP was detected. This is a real‑time active high pulse.

err_phy_tng

Output

When asserted, indicates a Link Training Error. This is a real‑time active high pulse.

err_phy_rcv

Output

When asserted, indicates a Receiver Error. This is a real‑time active high pulse.

root_err_reg_sts

Output

When asserted, indicates a a bit in the Root Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.

corr_err_reg_sts

Output

When set to 1, indicates that a bit in Correctable Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.

unc_err_reg_sts

Output

When set to 1, indicates that a bit in Uncorrectable Error Status register is set. The Application Layer can read this register using the LMI. This bit clears when read.