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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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11.5. Generating Traffic with the Test Engine IP
Every Intel Agilex® 7 M-Series FPGA EMIF design example includes an instance of the software-driven programmable AXI traffic generator, known as the Test Engine IP.
You can view the Test Engine IP software within the following Python scripts:
- A main.py file that parses the .qsys file and selects the traffic program to run during execution.
- A traffic_patterns.py file that contains many different tutorial programs and functional tests that you can refer to when writing your own traffic patterns.
For the EMIF design example, the hard-coded traffic program selected when you generate a design is the emif_tg_emulation traffic program, which provides these features:
- Single write and read (with AxLEN=axlen_a 1 )
- Single write and read (with AxLEN=axlen_b 2 )
- Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_a 1 )
- Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_b 2 )
- Random address 4 block of 512 writes and 512 reads (with AxLEN= axlen_a 1 )
1 | The axlen_a value is dependent on the memory technology:
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2 | The axlen_b value is dependent on the memory technology:
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3 | Sequential Address pattern starts at address=0, and increments by (AXI_DATA_WIDTH/8)*(AxLEN+1) on each transaction. |
4 | Random Address pattern starts at address=0, and uses pseudo-random addresses. |