Visible to Intel only — GUID: ewm1652955561010
Ixiasoft
Visible to Intel only — GUID: ewm1652955561010
Ixiasoft
7.9. Timestamp Registers
Word Offset | Register Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x0100 | tx_period_10G | Specifies the clock period for the timestamp adjustment on the datapaths. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
|
RW | 0x33333 |
0x0102 | tx_adj_fns_10G | Static timing adjustment in fractional nanoseconds on the transmit datapaths.
|
RW | 0x0 |
0x0104 | tx_adj_ns_10G | Static timing adjustment in nanoseconds on the transmit datapaths.
|
RW | 0x0 |
0x110 | tx_asymmetry | Specifies the asymmetry value and direction of arithmetic operation.
|
RW | 0x0 |
0x112 | tx_p2p | Specifies the direction of arithmetic operation for meanPathDelay.
|
RW | 0x0 |
0x114 | tx_cf_err_stat |
|
RW1C | 0x0 |
0x0120 | rx_period_10G | Specifies the clock period for the timestamp adjustment on the datapaths. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
|
RW | 0x33333 |
0x0122 | rx_adj_fns_10G | Static timing adjustment in fractional nanoseconds on the receive datapaths.
|
RW | 0x0 |
0x0124 | rx_adj_ns_10G | Static timing adjustment in nanoseconds on the receive datapaths.
|
RW | 0x0 |
0x12E | rx_p2p_mpd_ns | meanPathDelay valid and value in ns. The peer-to-peer mechanism delivers meanPathDelay for each ingress port. This needs to be added to the Sync packet’s correction field before the packet is sent out on egress port. Thus, the egress port might add any of the ingress ports' 'meanPathDelay'. The value to be added at the egress port should correspond to the ingress port on which the Sync packet has arrived.
|
RW | 0x0 |
0x130 | rx_p2p_mpd_fns | meanPathDelay value in fns.
|
RW | 0x0 |