Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

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ID 683814
Date 1/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines x
Intel® Arria® 10 GX and GT Pin Connection Guidelines Intel® Arria® 10 SX Pin Connection Guidelines Power Supply Sharing Guidelines for Intel® Arria® 10 Devices Document Revision History for the Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 GX and GT Pin Connection Guidelines x
Clock and PLL Pins Dedicated Configuration/JTAG Pins Optional/Dual-Purpose Configuration Pins Partial Reconfiguration Pins 3V Compatible I/O Pins Differential I/O Pins External Memory Interface and Hard Memory PHY Pins Reference Pins Voltage Sensor Pins Supply Pins Transceiver Pins Notes to Intel® Arria® 10 GX and GT Pin Connection Guidelines
Intel® Arria® 10 SX Pin Connection Guidelines x
HPS Supply Pins HPS Dedicated I/O Bank Pins HPS Peripheral Pins Shared 3V I/O Bank Pins Notes to Intel® Arria® 10 SX Pin Connection Guidelines
Power Supply Sharing Guidelines for Intel® Arria® 10 Devices x
Example 1— Intel® Arria® 10 GX Example 2— Intel® Arria® 10 GX Example 3— Intel® Arria® 10 GX Example 4— Intel® Arria® 10 GT Example 5— Intel® Arria® 10 GT Example 6— Intel® Arria® 10 GT Example 7— Intel® Arria® 10 GT Example 8— Intel® Arria® 10 SX Example 9— Intel® Arria® 10 SX Example 10— Intel® Arria® 10 SX Example 11— Intel® Arria® 10 GX (Using the SmartVID Feature) Notes to Power Supply Sharing Guidelines
Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

External Memory Interface and Hard Memory PHY Pins

Note: Intel® recommends that you create a Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 7.  External Memory Interface and Hard Memory PHY Pins
Pin Name Pin Functions Pin Description Connection Guidelines
DQS[#] I/O,bi-directional Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[#] I/O,bi-directional Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQ[#] I/O,bi-directional Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Connect unused pins as defined in the Intel® Quartus® Prime software.
CQ[#] I/O, Input Optional data strobe signal for use in QDRII/II+/II+ Xtreme SRAM. These are the pins for echo clocks. Connect unused pins as defined in the Intel® Quartus® Prime software.
CQn[#] I/O, Input Optional complementary data strobe signal for use in QDRII/II+/II+ Xtreme SRAM. These are the pins for echo clocks. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQS[#]_[#] I/O, bidirectional Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQSn[#]_[#] I/O, bidirectional Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Connect unused pins as defined in the Intel® Quartus® Prime software.
DQ[#]_[#]_[#] I/O, bidirectional Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important. However, if you plan on migrating to a different memory interface that has a different DQ bus width, you will need to reevaluate your pin assignments. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Connect unused pins as defined in the Intel® Quartus® Prime software.
CQ[#]_[#]/CQn[#]_[#] I/O, Input Optional data strobe signal for use in QDRII/II+/II+ Xtreme SRAM. These are the pins for echo clocks. Connect unused pins as defined in the Intel® Quartus® Prime software.
QK[#]_[#] I/O, Input Optional data strobe signal for use in RLDRAM 3. Connect unused pins as defined in the Intel® Quartus® Prime software.
QKn[#]_[#] I/O, Input Optional complementary data strobe signal for use in RLDRAM 3. Connect unused pins as defined in the Intel® Quartus® Prime software.
DM[#]_[#] I/O, Output Optional write data mask, edge-aligned to DQ during write. Connect unused pins as defined in the Intel® Quartus® Prime software.
RESET_N_0 I/O, Output Active low reset signal. Connect unused pins as defined in the Intel® Quartus® Prime software.
A_[#] I/O, Output Address input for DDR3, DDR4, QDRII/II+/II+ Xtreme SRAM, and RLDRAM3. Connect unused pins as defined in the Intel® Quartus® Prime software.
BA_[#] I/O, Output Bank address input for DDR2, DDR3, and RLDRAM 3. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK_[#] I/O, Output Input clock for external memory devices. Connect unused pins as defined in the Intel® Quartus® Prime software.
CK_N_[#] I/O, Output Input clock for external memory devices, inverted CK. Connect unused pins as defined in the Intel® Quartus® Prime software.
CKE_[#] I/O, Output High signal enables clock, low signal disables clock. Connect unused pins as defined in the Intel® Quartus® Prime software.
CS_N_[#] I/O, Output Active low chip select. Connect unused pins as defined in the Intel® Quartus® Prime software.
REF# I/O, Output Auto-refresh control input for RLDRAM 3. Connect unused pins as defined in the Intel® Quartus® Prime software.
ODT_[#] I/O, Output On die termination signal to set the termination resistors to each pin. Connect unused pins as defined in the Intel® Quartus® Prime software.
WE_N_0 I/O, Output Write-enable input for DDR3 SDRAM, RLDRAM 3, and all supported protocols. Connect unused pins as defined in the Intel® Quartus® Prime software.
CAS_N_0 I/O, Output Column address strobe for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
RAS_N_0 I/O, Output Row address strobe for DDR3 SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
RPS_N_0 I/O, Output Read signal to QDRII/II+/II+ Xtreme memory. Active low and reset in the inactive state. Connect unused pins as defined in the Intel® Quartus® Prime software.
WPS_N_0 I/O, Output Write signal to QDRII/II+/II+ Xtreme memory. Active low and reset in the inactive state. Connect unused pins as defined in the Intel® Quartus® Prime software.
ALERT_N_0 I/O, Input Alert input that indicate to the system's memory controller that a specific alert or event has occurred.

Connect unused pins as defined in the Intel® Quartus® Prime software.

If you are using the Early I/O Release feature in the Intel® Arria® 10 SX devices, ensure that this pin is located within the active HPS I/O banks. For more information, refer to the HPS EMIF Design Consideration chapter of the Intel® Arria® 10 SoC Design Guidelines.

PAR_0 I/O, Output Command and Address Parity Output: DDR4 supports even parity check in DRAMs with MR setting. Once PAR is enabled via Register in MR5, then DRAM calculates parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,BG0-BG1,BA0-BA1,A17-A0. Output parity should maintain at the rising edge of the clock and at the same time with command and address with CS_n low. Connect unused pins as defined in the Intel® Quartus® Prime software.
ACT_N_0 I/O, Output Command output that indicates an ACTIVATE command. Applies for DDR4. Connect unused pins as defined in the Intel® Quartus® Prime software.
BG_[#] I/O, Output Bank group address outputs that define the bank group to which a REFRESH, ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Applies for DDR4. Connect unused pins as defined in the Intel® Quartus® Prime software.
C_[#] I/O, Output Stack address inputs that are used when devices are stacked. Applies for DDR4. Connect unused pins as defined in the Intel® Quartus® Prime software.
RM_[1,0] I/O, Output Rank multiplication. Connect unused pins as defined in the Intel® Quartus® Prime software.
PE_N_0 I/O, Input Address parity error. Connect unused pins as defined in the Intel® Quartus® Prime software.
AP_0 I/O, Output Address parity. Connect unused pins as defined in the Intel® Quartus® Prime software.
AINV_0 I/O, Output Address inversion state for address bus. Connect unused pins as defined in the Intel® Quartus® Prime software.
RW[A,B]_N_0 I/O, Output Synchronous read/write input. Connect unused pins as defined in the Intel® Quartus® Prime software.
DOFF_N_0 I/O, Output Phase-locked loop (PLL) turn off for QDR II/ II + SDRAM. Connect unused pins as defined in the Intel® Quartus® Prime software.
LD[A,B]_N_0 I/O, Output Synchronous load input. Connect unused pins as defined in the Intel® Quartus® Prime software.
REF_N_0 I/O, Output Auto-refresh control input for RLDRAM 3. Connect unused pins as defined in the Intel® Quartus® Prime software.
CFG_N_0 I/O, Output Configuration bit. Connect unused pins as defined in the Intel® Quartus® Prime software.
LBK[#]_N_0 I/O, Output Loop-back mode. Connect unused pins as defined in the Intel® Quartus® Prime software.
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