JESD204B Intel FPGA IP Release Notes

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Date 12/16/2019
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v19.2.0 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.1 1.4. JESD204B Intel FPGA IP v18.1 1.5. JESD204B Intel FPGA IP v18.0 1.6. JESD204B IP Core v17.1 1.7. JESD204B IP Core v17.0 1.8. JESD204B IP Core v16.1 1.9. JESD204B IP Core v16.0 1.10. JESD204B IP Core v15.1 1.11. JESD204B IP Core v15.0 1.12. JESD204B IP Core v14.1 1.13. JESD204B Intel® FPGA IP User Guide Archives 1.14. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.12. JESD204B IP Core v14.1

Table 13.  14.1 December 2014
Description Impact
Revised the parameter name of Enable PLL/CDR Dynamic Reconfiguration to Enable Transceiver Dynamic Reconfiguration. –
Added a new parameter—Altera Debug Master Endpoint. Enable this feature to access the reconfiguration space of the Transceiver Native PHY IP Core. This feature is available only for Arria 10 device family.
Added new register bits:
  • TX core:
    • Bit: csr_reinit_w_rxsyncn_rise in the dll_ctrl register (offset 0x50).
    • Description: This bit controls the Code Group Synchronization (CGS) state exit behavior during link re-initialization.
  • RX core:
    • Bit: csr_syncn_delay in the syncn_sysref_ctrl register (offset 0x54).
    • Description: This bit extends the SYNC_N assertion (low state) by delaying the deassertion.

The new register bits are available when you upgrade the IP core in your design to v14.1.

Updated the test_ilas_loop bit behavior in the dll_ctrl register (offset 0x50).

Upgrade the IP core in your design to v14.1 to implement this new behavior.

Changed the JESD204B Avalon-MM slave interface readLatency value from 0 to 1.

Upgrade the IP core in your design to v14.1 to implement this new behavior.

If you upgrade your IP core in your design, you have to reconnect the IP core in your design due to port change.

Changed the interface type of the jesd204_rx_int and jesd204_tx_int signals from conduit to interrupt. –
Changed signal type of pll_locked, tx_cal_busy, rx_cal_busy, and rx_is_lockedtodata. –
New simulation flow for the IP core design example testbench. Changed the link bring up sequence by powering up the JESD204B TX link and JESD204B RX link independently.

Regenerate the design example from the IP Parameter Editor to obtain this change.

Changed the default value of the 8B/10B encoder to /K28.5/ control word during reset assertion to resolve the CDR lock issue in the receiver. This change only affects design that select Enabled Soft PCS for the PCS Option parameter.

If you use Enabled Soft PCS for the PCS Option parameter, you must upgrade the IP core in your design to v14.1.

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