Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.2. 10/100/1000 Ethernet PHY

The Intel® Stratix® 10 GX FPGA development board supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Intel Triple-Speed Ethernet Intel® FPGA IP core MAC function. The PHY-to-MAC interface employs SGMII using the Intel® Stratix® 10 GX FPGA LVDS pins in Soft-CDR mode at 1.25 Gbps transmit and receive. In 10 Mb or 100 Mb mode, the SGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times. The MAC function must be provided in the FPGA for typical networking applications.

The Marvell 88E1111 PHY uses a 2.5V and 1.0V power rails and requires a 25 MHz reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper lines with Ethernet traffic.

Figure 9. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
Table 17.  Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference (U13) Schematic Signal Name FPGA Pin Number I/O Standard Description
23 ENET_INTn AC35 3.0V Management bus interrupt
25 ENET_MDC AD35 3.0V Management bus data clock
24 ENET_MDIO AD34 3.0V Management bus data
28 ENET_RESETn AB34 3.0V Device reset
76 ENET_LED_LINK10 – 2.5V 10 Mb link LED
74 ENET_LED_LINK100 – 2.5V 100 Mb LED
73 ENET_LED_LINK1000 – 2.5V 1000 Mb link LED
69 ENET_LED_RX – 2.5V RX data active LED
68 ENET_LED_TX – 2.5V TX data active LED
75 ENET_RX_N AW25 LVDS SGMII receive channel
77 ENET_RX_P AV25 LVDS SGMII receive channel
81 ENET_TX_N AT25 LVDS SGMII transmit channel
82 ENET_TX_P AU25 LVDS SGMII transmit channel
55 ENET_XTAL_25MHZ – 2.5V 25 MHz RGMII transmit clock
31 MDI_N0 – 2.5V Media dependent interface
34 MDI_N1 – 2.5V Media dependent interface
41 MDI_N2 – 2.5V Media dependent interface
43 MDI_N3 – 2.5V Media dependent interface
29 MDI_P0 – 2.5V Media dependent interface
33 MDI_P1 – 2.5V Media dependent interface
39 MDI_P2 – 2.5V Media dependent interface
42 MDI_P3 – 2.5V Media dependent interface
Level Two Title