AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683652
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204C Intel® FPGA IP and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 927: JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer (TL) 1.3.3. Deterministic Latency - Subclass 1 (DL)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Sync Header Alignment (SHA) 1.3.1.2. Extended Multiblock Alignment (EMBA)
1. JESD204C Intel® FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel® Stratix® 10 E-tile Devices

1.3.1.2. Extended Multiblock Alignment (EMBA)

Table 2.  Extended Multiblock Alignment Test Cases
Test Case Objective Description Passing Criteria
EMBA.1 Check if the Extended Multiblock Lock is asserted only after the assertion of Sync Header Lock. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_emb_lock
  • j204c_rx_sh_lock
  • j204c_rx_int 0

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_emb_lock is asserted after assertion of j204c_rx_sh_lock.
  • The j204c_rx_int 0 signal is deasserted if there is no error.
EMBA.2 Check if the Extended Multiblock Lock status being stable (after extended multiblock lock or until elastic buffer is released) along with no invalid multiblock. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_emb_lock
  • j204c_rx_int 0

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_emb_lock should remain asserted.
  • The j204c_rx_int 0 signal is deasserted if there is no error.
EMBA.3 Check the lane alignment. The following signals in <ip_variant_name> _base.v are tapped:
  • j204c_rx_dev_lane_align
  • j204c_rx_int 0

The rxlink_clk is used as the sampling clock for the Signal Tap.

  • The j204c_rx_dev_lane_align is asserted after the assertion of j204c_rx_emb_lock and next LEMC event.
  • The j204c_rx_int 0 signal is deasserted if there is no error.
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