AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.2.2. Transmit and Receive Width Adapters

The transmit width adapter block is used to convert the input data width in the soft PCS from 32 bits to 64 bits (with 8b/10b encoding) or 80 bits (without 8b/10b encoding) for data rates of 4.9152 Gbps and above. The same block is reused for lower data rates in auto rate negotiation. For data rates of 3.072 Gbps or below, the transmit width adapter converts the data width from 32 bits to 16 bits (with 8b/10b encoding) or 20 bits (without 8b/10b encoding). Because the PMA direct interface mode has a minimum frequency limitation, data width conversion is required.

Similarly, the receive width adapter block reverses the data width from 64 bits (with 8b/10b encoding) or 80 bits (without 8b/10b encoding) to 32 bits for data rates of 4.9152 Gbps and above. For data rates of 3.072 Gbps or below, the receive width adapter converts the data width from 16 bits (with 8b/10b enconding) or 20 bits (without 8b/10b encoding) to 32 bits.

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