Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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ID 683588
Date 12/01/2017
Public
Document Table of Contents
Document Table of Contents x
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Document Revision History

Date Version Changes Made
2017.12.01 17.1.0
  • Updated for Intel® Quartus® Prime Pro Edition and Intel® Cyclone® 10 devices.
  • Updated steps to use .sdc file rather that GUI for constraint entry.
  • Consolidated related steps.
  • Updated all screenshots.
  • Updated for latest Intel® branding and style conventions.
2017.12.05 1.2 Converted to new Template, updated for most recent devices.
December 2009 1.1 Updated figures in Chapter 2.

Updated chapter for Intel® Quartus® Prime software 9.1 functionality.

May 2006 1.0 Initial Release
Level Two Title