Intel® FPGA RTE for OpenCL™ Standard Edition: Getting Started Guide

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ID 683550
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide 2. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for 64-Bit Windows 3. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for x86_64 Linux Systems 4. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for Intel® ARMv7-A SoC FPGA A. Document Revision History of the Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide
1. Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide x
1.1. Prerequisites for the Intel® FPGA RTE for OpenCL™ Standard Edition 1.2. Contents of the Intel® FPGA RTE for OpenCL™ Standard Edition 1.3. RTE Utility 1.4. Overview of the Intel® FPGA RTE for OpenCL™ Standard Edition Setup Process
1.3. RTE Utility x
1.3.1. Displaying the Software Version 1.3.2. Listing the Intel® FPGA RTE for OpenCL™ Standard Edition Utility Command Options 1.3.3. Managing an FPGA Board 1.3.4. Managing Host Application
2. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for 64-Bit Windows x
2.1. Downloading the Intel® FPGA RTE for OpenCL™ Standard Edition 2.2. Installing the Intel® FPGA RTE for OpenCL™ 2.3. Setting the Intel® FPGA RTE for OpenCL™ Standard Edition User Environment Variables 2.4. Verifying Software Installation 2.5. Installing an FPGA Board 2.6. Updating the Hardware Image on the FPGA 2.7. Executing an OpenCL Kernel on an FPGA 2.8. Uninstalling the Software 2.9. Uninstalling the FPGA Board
2.6. Updating the Hardware Image on the FPGA x
2.6.1. Querying the Device Name of Your FPGA Board 2.6.2. Programming the Flash Memory of an FPGA
2.7. Executing an OpenCL Kernel on an FPGA x
2.7.1. Building the Host Application 2.7.2. Running the Host Application 2.7.3. Output from Successful Kernel Execution
3. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for x86_64 Linux Systems x
3.1. Downloading the Intel® FPGA RTE for OpenCL™ Standard Edition 3.2. Installing the Intel® FPGA RTE for OpenCL™ 3.3. Setting the Intel® FPGA RTE for OpenCL™ Standard Edition User Environment Variables 3.4. Verifying Software Installation 3.5. Installing an FPGA Board 3.6. Updating the Hardware Image on the FPGA 3.7. Executing an OpenCL Kernel on an FPGA 3.8. Uninstalling the Software 3.9. Uninstalling the FPGA Board
3.6. Updating the Hardware Image on the FPGA x
3.6.1. Querying the Device Name of Your FPGA Board 3.6.2. Programming the Flash Memory of an FPGA
3.7. Executing an OpenCL Kernel on an FPGA x
3.7.1. Building the Host Application 3.7.2. Running the Host Application 3.7.3. Output from Successful Kernel Execution
4. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for Intel® ARMv7-A SoC FPGA x
4.1. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for SoC FPGA on Windows 4.2. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for SoC FPGA on Linux
4.1. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for SoC FPGA on Windows x
4.1.1. Downloading the Intel® FPGA SDK for OpenCL Standard Edition and the SoC EDS Standard Edition 4.1.2. Installing the Intel® FPGA SDK for OpenCL Standard Edition for SoC FPGA 4.1.3. Installing the Intel® SoC FPGA Embedded Development Suite Standard Edition 4.1.4. Recompiling the Linux Kernel Driver 4.1.5. Installing the Intel FPGA RTE for OpenCL Standard Edition onto the SoC FPGA Board 4.1.6. Installing the Cyclone V SoC Development Kit 4.1.7. Executing an OpenCL Kernel on an SoC FPGA 4.1.8. Uninstalling the Intel® FPGA RTE for OpenCL™ Standard Edition
4.1.6. Installing the Cyclone V SoC Development Kit x
4.1.6.1. Writing an SD Card Image onto the Micro SD Flash Card 4.1.6.2. Configuring the SW3 Switches 4.1.6.3. Setting Up Terminal Connection 4.1.6.4. Setting Environment Variables and Loading OpenCL Linux Kernel Driver 4.1.6.5. Connecting the Board to Network via Ethernet
4.1.6.5. Connecting the Board to Network via Ethernet x
4.1.6.5.1. Ensuring IP Address Acquisition 4.1.6.5.2. Using SSH and SCP
4.1.7. Executing an OpenCL Kernel on an SoC FPGA x
4.1.7.1. Building the Host Application 4.1.7.2. Running the Host Application 4.1.7.3. Output from Successful Kernel Execution on the Cyclone V SoC Development Kit
4.2. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for SoC FPGA on Linux x
4.2.1. Downloading the Intel® FPGA SDK for OpenCL™ Standard Edition and the SoC EDS Standard Edition 4.2.2. Installing the Intel® FPGA SDK for OpenCL Standard Edition for SoC FPGA 4.2.3. Installing the Intel® SoC FPGA Embedded Development Suite Standard Edition 4.2.4. Recompiling the Linux Kernel Driver 4.2.5. Installing the Intel FPGA RTE for OpenCL Standard Edition onto the SoC FPGA Board 4.2.6. Installing the Cyclone V SoC Development Kit 4.2.7. Executing an OpenCL Kernel on an SoC FPGA 4.2.8. Uninstalling the Intel® FPGA RTE for OpenCL™ Standard Edition
4.2.6. Installing the Cyclone V SoC Development Kit x
4.2.6.1. Writing an SD Card Image onto the Micro SD Flash Card 4.2.6.2. Configuring the SW3 Switches 4.2.6.3. Setting Up Terminal Connection 4.2.6.4. Setting Environment Variables and Loading OpenCL Linux Kernel Driver 4.2.6.5. Connecting the Board to Network via Ethernet
4.2.6.5. Connecting the Board to Network via Ethernet x
4.2.6.5.1. Ensuring IP Address Acquisition 4.2.6.5.2. Mounting a Shared Drive 4.2.6.5.3. Using SSH and SCP
4.2.7. Executing an OpenCL Kernel on an SoC FPGA x
4.2.7.1. Building the Host Application 4.2.7.2. Running the Host Application 4.2.7.3. Output from Successful Kernel Execution on the Cyclone V SoC Development Kit
1. Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide
2. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for 64-Bit Windows
3. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for x86_64 Linux Systems
4. Getting Started with the Intel® FPGA RTE for OpenCL™ Standard Edition for Intel® ARMv7-A SoC FPGA
A. Document Revision History of the Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide

A. Document Revision History of the Intel® FPGA RTE for OpenCL™ Standard Edition Getting Started Guide

Document Version Intel® Quartus® Prime Version Changes
2018.09.24 18.1
  • Replaced altera.com links with intel.com links.
2018.05.04 18.0

  • Removed information related to the Intel FPGA RTE for OpenCL Pro Edition, the Intel FPGA SDK for OpenCL Pro Edition, and the Intel SoC FPGA Embedded Development Suite Pro Edition.

Date Version Changes
November 2017 2017.11.04
  • Rebranded the following:
    • ALTERAOCLSDKROOT to INTELFPGAOCLSDKROOT
    • CL_CONTEXT_EMULATOR_DEVICE_ALTERA to CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA
  • In Prerequisites of the Intel® FPGA RTE for OpenCL™ , changed Microsoft Visual Studio version 2010 Professional as Microsoft Visual Studio Professional version 2010 or later.
  • In Building the Host Application (Windows), updated references to Microsoft Visual Studio 2015 as Microsoft Visual Studio.
May 2017 2017.05.05
  • Rebranded the Altera Client Driver (ACD) to FPGA Client Driver (FCD).
  • Updated the download instructions in Downloading the Intel® FPGA RTE for OpenCL™ for Windows and Linux.
  • Added reminders that folder names where you uncompress downloaded OpenCL design examples must not contain spaces.
October 2016 2016.10.31
  • Rebranded Altera RTE for OpenCL to Intel® FPGA RTE for OpenCL™ .
  • Rebranded Altera SoC Embedded Design Suite to Intel SoC FPGA Embedded Design Suite.
  • Rebranded ARM DS-5 Altera Edition Toolkit to Arm* DS-5* for Intel® SoC FPGA Edition Toolkit.
  • Deprecated and removed support for big-endian system, resulting in the following documentation changes:
    • In Prerequisites for the Altera RTE for OpenCL, removed "Red Hat Enterprise Linux 6 on big-endian system" from the list of supported operating systems.
    • In Contents of the Altera RTE for OpenCL, removed the Big-Endian System Directory column from the table of contents in the RTE installation directory.
    • In Downloading the Altera RTE for OpenCL for Linux, removed from Step 6 the choice to select the OpenCL PowerPC RPM installation package.
    • Removed the topics Installing the Altera RTE for OpenCL on Big-Endian Systems and Setting the Environment Variables on Big-Endian Systems.
    • In Installing and FPGA Board for Linux, removed information on running the init_opencl script on big-endian systems, and removed related link to Setting the Environment Variables on Big-Endian Systems.

  • In Installing an FPGA Board for 64-bit Windows and Linux, provided the following updates:

    • Noted that the SDK supports installation of multiple Custom Platforms. To use the SDK utilities on each board in a system with multiple Custom Platforms, the AOCL_BOARD_PACKAGE_ROOT environment variable setting must correspond to the Custom Platform subdirectory of the associated board.
    • Noted that in a system with multiple Custom Platforms, the host program should use ACD to discover the boards instead of directly linking to the MMD libraries.
  • In Building the Host Application for 64-bit Windows, outlined the prerequisite tasks for setting up ACD and ICD for use with Microsoft Visual Studio 2015 prior to building the host application.
  • Updated all RTE output for a successful kernel execution.
May 2016 2016.05.02
  • Replaced the lists of supported Windows and Linux versions to a link to the Operating System Support page on the Altera website.
  • Added the %ALTERAOCLSDKROOT%\windows64\bin setting to the list of Windows environment variables.
November 2015 2015.11.02
  • Added Windows 8.1 to supported Windows versions.
  • Added the following figures to illustrate the RTE setup processes for x86-64, big-endian, and SoC systems:
    • RTE Setup Process for x86-64 and Big-Endian Systems
    • RTE Setup Process for SoC
  • Modified software download and installation instructions for SoC to included the new tar file installation package.
  • Modified instructions for executing the hello_world OpenCL example design onto a device. You must create your own .aocx file from the hello_world.cl file on a separate development machine, and then use the RTE to deploy the .aocx file onto the device.
  • Removed licensing sections because an AOCL license is not necessary to run the RTE.
May 2015 15.0.0
  • Reorganized instructions into the following sections:
    • Introduction to the RTE
    • Getting Started with the RTE for Windows
    • Getting Started with the RTE for Linux and Big-Endian Systems
    • Getting Started with the RTE for Altera ARMv7-A SoC, which is further divided into Windows and Linux instructions
December 2014 14.1.0
  • Reorganized information flow.
  • Updated Red Hat Enterprise Linux (RHEL) version support.
  • Added licensing information in the Licensing the Software section.
  • Included information on the init_opencl script for setting environment variables.
  • Updated the board uninstallation instructions to include the invocation of the aocl uninstall utility command.
June 2014 14.0.0 Initial release.
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