RapidIO II Intel® FPGA IP Release Notes

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ID 683549
Date 9/28/2020
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Product Discontinuance Notification 1. RapidIO II Intel® FPGA IP Release Notes
1. RapidIO II Intel® FPGA IP Release Notes x
1.1. RapidIO II IP v19.2.0 1.2. RapidIO II Intel® FPGA IP v18.0 1.3. RapidIO II IP Core v17.1 1.4. RapidIO II IP Core v15.1 1.5. RapidIO II IP Core v14.1 1.6. RapidIO II IP Core v14.0 Arria 10 Edition 1.7. RapidIO II IP Core v14.0 1.8. RapidIO II IP Core v13.1 1.9. RapidIO II IP Core v13.0 1.10. RapidIO II IP Core User Guide Archives
Product Discontinuance Notification
1. RapidIO II Intel® FPGA IP Release Notes

1.6. RapidIO II IP Core v14.0 Arria 10 Edition

Table 6.  Version 14.0 Arria 10 Edition August 2014
Description Impact Note
Verified in the Quartus II software v14.0 Arria 10 Edition. (Added support for Arria 10 devices). Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design.
Arria 10 variations require that you instantiate and connect a TX transceiver PLL IP core in your design. Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design. The new interface signals are listed in the RapidIO II IP Core Signal Changes table.
Arria 10 variations do not require that you instantiate and connect a dynamic reconfiguration controller. Instead, if you turn on the new parameter Enable transceiver dynamic reconfiguration, these variations have an internal reconfiguration controller that the user accesses through an Avalon-MM interface. Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design. The new interface signals are listed in the RapidIO II IP Core Signal Changes table.
Table 7.  RapidIO II IP Core Signal ChangesSignals added or modified in version 14.0 Arria 10 Edition.
Old Signal Name New Signal Name Notes
— tx_bonded_clocks_ch<n>[5:0] New interface to external TX PLL. Relevant for Arria 10 variations only.

Individual transceiver channel clock signals. One signal (_ch<n>) for each RapidIO lane <n>.

— reconfig_clk_ch<n> New Arria 10 transceiver reconfiguration interface. This interface is available if you turn on Enable transceiver dynamic reconfiguration in the RapidIO II parameter editor. Relevant for Arria 10 variations only.

One signal (_ch<n>) for each RapidIO lane <n>.

— reconfig_reset_ch<n>
— reconfig_read_ch<n>
— reconfig_write_ch<n>
— reconfig_address_ch<n>[9:0]
— reconfig_readdata_ch<n>[31:0]
— reconfig_waitrequest_ch<n>
— reconfig_writedata_ch<n>[31:0]
reconfig_to_xcvr Not present in Arria 10 variations. Transceiver reconfiguration interface signals for specific non-Arria 10 device families (as supported in past and future versions of the Quartus II software). These signals are not present in Arria 10 variations.
reconfig_from_xcvr Not present in Arria 10 variations.
pll_locked Not present in Arria 10 variations.
pll_powerdown Not present in Arria 10 variations.
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