Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 3/26/2019
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Intel® Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

2.2.4.1. SMH File Types

The .smh is an Intel-format hexadecimal file. You can generate the following .smh file revisions:

  • Revision 1—Generated for Stratix® IV and Arria® II devices. This revision does not support hierarchy tagging, and does not contain tag size or region map information.
  • Revision 2—Generated for Stratix® V, Arria® V, and Cyclone® V devices. The generated .smh contains tag size and region map information.
  • Revision 3—Generated for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. The generated .smh contains tag size and region map information, and can accommodate longer sensitivity data addresses.

Revision 1 SMH

In revision 1 files, the sensitivity map header provides basic information about the .smh format. This information includes the base addresses for the frame information, offset maps and length of the single offset map, and the sensitivity data array.

Figure 6. Revision 1 SMH

Revision 1 files contain the following arrays:

  • Frame information array—Contains a 32 bit string for each frame in the device. The frame number serves as the index for the frame information string. Each frame information string provides the following information:
    • offset_map_array_index (Bits 7:0)—Index for the offset map array that this frame uses.
    • frame_info_data_offset (Bits 31:8)—24 bit address offset into the sensitivity array for this frame.
    Note: For Stratix® IV and Arria® II devices, the frame information array lists CRAM and embedded RAM frame strings. However, the .smh sets the embedded RAM frame string to 0xFFFFFFF in the frame information array entry because the EDCRC circuitry and sensitivity processing only correct CRAM frames. For all other device families, the frame information array lists only the CRAM frame strings.
  • Offset map array—The offset map information array is a set of arrays containing 16 bit offset maps. Each offset map value represents an additional offset into the sensitivity array for a frame group. Each offset map value is 16 bits. The offset_map_length string in the header information defines the size of each offset map array.
  • Sensitivity data array—The sensitivity data array is a flat-bit vector where 1 specifies a sensitive bit and 0 specifies an insensitive bit.

Revision 2 SMH

In revision 2 files, the sensitivity map header is an extension of revision 1 header format. The header information provides basic information about the .smh revision 2, and includes all the revision 1 header information fields. The additional fields include size of the sensitivity data tag size in bits, base addresses for the region map, and 32 bit CRC signature of the corresponding .sof file.

Figure 7. Revision 2 SMH

The 32 bit ID of the sensitivity map header revision 2 is defined as follows:

  • Bits 23:0— Intel® FPGA sensitivity map header ID 0x445341
  • Bits 24:27—Bit mask for the header information
    • Bit 24—Reserved
    • Bit 25—Indicates the presence of sensitivity tag information in the .smh file
    • Bit 26:27—Reserved
  • Bit 28—Indicates the presence of a 32 bit CRC signature of a corresponding .sof
  • Bits 29:31—Reserved

Revision 2 files contain the following arrays:

  • Frame information array—Contains a 32 bit string for each frame in the device. The frame number serves as the index for the frame information string. Each frame information string provides the following information:
    • offset_map_array_index (bits 7:0)—Index for the offset map array that this frame uses.
    • frame_info_data_offset (bits 31:8)—24-bit address offset into the sensitivity array for this frame.
  • Offset map array—The offset map information array is a set of arrays containing 16 bit offset maps. Each offset map value represents an additional offset into the sensitivity array for a frame group. Each offset map value is 16 bits. The size of each offset map array is defined by the offset_map_length string contained in the header information.
  • Sensitivity data array—The size of the single sensitivity data entry or tag (sensitivity_data_tag_size) is in bits and aligned to power of 2. The sensitivity data array is a flat sensitivity tag vector where a sensitive tag of 0 specifies a bit insensitive for all regions, and non-zero tag specifies an offset into region map.
  • Region map information array—The region map information array contains a 16-bit string for each non-zero sensitivity tag. The sensitivity data tag serves as the index-1 for the region map array. The string is a bitmask of the regions, the bit is sensitive for. Each region can be identified in the bitmask by mask 1 << (Region ID - 1).
Table 4.  Revision 2 SMH File Size and ASD Regions Based on Sensitivity Tag These SMH sizes are for Stratix V 5SGXEA7 device with a SOF size of 31,731,193 bytes.
Number of ASD Regions Sensitivity Tag Size (bits) SMH Size (bytes)
1 1 2,296,736
2-3 2 3,984,920
3-15 4 7,361,308
10-127 8 14,114,024

Revision 3 SMH

The revision 3 SMH file format is an extension of the revision 2 header format that accomodates longer sensitivity data addresses.
Figure 8. Revision 3 SMH

The file header information is the same as in revision 2, except it has a different 32 bit ID: 0xX6445341. The sensitivity map header definition 32 bit ID is the same as revision 2 except bit 26 indicates the usage of longer sensitivity data addresses.

The frame information array contains a 48 bit entry for each frame in the device. Like revision 2, the frame number serves as the index for the frame information entry. Each frame information entry contains:

  • offset_map_array_index—Bits [47:32] are the 16 bit index for the offset map array.
  • frame_info_data_offset—Bits [31:0] are the 32 bit address offset into the sensitivity array for sensitivity_data_tag_size = 1.

The offset map array, sensitivity data array, and region map information array have the same definition as revision 2.

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