AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Public
Document Table of Contents

1.2.1. Hardware and Software Requirements

The reference design requires and uses the following hardware and software tools:

  • Intel® Stratix® 10 GX FPGA development board with the DDR4 module connected to Hi-Lo interface
  • Linux Operating System - kernel version 3.10 or above
  • Super user access on the host machine
  • PCIe* slot to plug-in the Intel® Stratix® 10 GX FPGA development board
  • Open source driver for this PR over PCIe* reference design
  • Intel® Quartus® Prime Pro Edition software v.18.1
  • Intel® FPGA Download Cable driver
Important:
  • The Linux driver accompanying this reference design is not a production driver. You must adapt this driver to your design’s strategy to handle backpressure from the Intel® Stratix® 10 Partial Reconfiguration IP core.
  • This reference design works under the assumption that the PCIe* link does not require a 100 ms initialization time.
Note: The open source driver developed for this PR over PCIe* reference design is tested using CentOS 7.