Intel® Arria® 10 FPGA Development Kit User Guide

Download PDF
ID 683526
Date 1/13/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 FPGA Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Update Portal 6. Board Components A. Additional Information
1. Intel® Arria® 10 FPGA Development Kit Overview x
1.1. General Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Subscription Edition Software 2.2. Development Kit Package 2.3. Installing the USB-Blaster Driver
2.1. Installing the Subscription Edition Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings 3.3. Default Switch and Resistor Settings 3.4. Factory Reset
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The Flash Tab 4.4.5. The XCVR Tab 4.4.6. The PCIe Tab 4.4.7. The FMC A Tab 4.4.8. The FMC B Tab 4.4.9. The DDR3 Tab 4.4.10. The DDR4 Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page
5.1. Connecting to the Board Update Portal Web Page x
5.1.1. Using the Board Update Portal to Update User Designs
6. Board Components x
6.1. Board Overview 6.2. MAX V CPLD System Controller 6.3. FPGA Configuration 6.4. Status Elements 6.5. User Input/Output 6.6. Clock Circuitry 6.7. Components and Interfaces 6.8. Memory 6.9. Board Power Supply 6.10. Daughtercards
6.3. FPGA Configuration x
6.3.1. Configuring the FPGA Using Programmer
6.5. User Input/Output x
6.5.1. User-Defined Push Buttons 6.5.2. User-Defined DIP Switch 6.5.3. User-Defined LEDs 6.5.4. Character LCD 6.5.5. DisplayPort 6.5.6. SDI Video Input/Output Ports
6.6. Clock Circuitry x
6.6.1. On-Board Oscillators 6.6.2. Off-Board Clock I/O
6.7. Components and Interfaces x
6.7.1. PCI Express 6.7.2. 10/100/1000 Ethernet PHY 6.7.3. HiLo External Memory Interface 6.7.4. FMC 6.7.5. QSFP 6.7.6. SFP+ 6.7.7. I2C
6.8. Memory x
6.8.1. Flash 6.8.2. Programming the Flash Using Intel® Quartus® Prime Programmer
6.9. Board Power Supply x
6.9.1. Power Distribution System 6.9.2. Power Measurement
6.10. Daughtercards x
6.10.1. External Memory Interface
6.10.1. External Memory Interface x
6.10.1.1. DDR3L 6.10.1.2. DDR4 6.10.1.3. RLDRAM 3 6.10.1.4. QDR-IV 6.10.1.5. FMC Loopback Card
6.10.1.5. FMC Loopback Card x
6.10.1.5.1. High Pin Count (HBC) 6.10.1.5.2. Low Pin Count (LPC)
A. Additional Information x
A.1. Document Revision History for the Intel® Arria® 10 FPGA Development Kit User Guide A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Intel® Arria® 10 FPGA Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Update Portal
6. Board Components
A. Additional Information

5.1. Connecting to the Board Update Portal Web Page

This section provides instructions to connect to the Board Update Portal web page. Before you proceed, ensure that you have the following:

  • A PC with a connection to a working Ethernet port on a DHCP enabled network.
  • A separate working Ethernet port connected to the same network for the board.
  • The Ethernet cable, power cables, and development board that are included in the kit.

To connect to the Board Update Portal web page, perform these steps:

  1. Install the latest Intel® software tools, including the Intel® Quartus® Prime software, Nios® II processor and IP functions. If necessary, download the Intel® Quartus® Prime Lite Edition software.
  2. With the board powered down, set SW6.4 to the ON position.
  3. Attach the Ethernet cable from the board to your LAN.
  4. Power up the board. The board connects to the LAN's gateway router and obtains an IP address. The LCD on the board will display the IP address.
  5. Launch a web browser on the PC that is connected to the same network, and enter the IP address from the LCD into the browser address bar. The Board Update Portal web page will appear in the browser.

You can click Intel® Arria® 10 GX FPGA Development Kit on the Board Update Portal web page to access the kit’s home page for documentation updates and additional new designs.

You can also navigate directly to the Intel® Arria® 10 GX FPGA Development Kit page of the Intel® website to determine if you have the latest kit software.


Section Content
Using the Board Update Portal to Update User Designs

Related Information
Level Two Title