2.3. Agilex™ 7 FPGAs and SoCs M-Series

Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458

Date 4/01/2024

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Table 13. M-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device	Logic Element	Adaptive Logic Module	M20K		MLAB		HBM2E DRAM (GB)	DSP		Crypto Block
Device	Logic Element	Adaptive Logic Module	Count	Size (Mb)	Count	Size (Mb)	HBM2E DRAM (GB)	Count	18x19 Multiplier	Crypto Block
AGM 032	3,245,000	1,100,000	15,932	311	55,000	33	16 / 32	9,375	18,750	—
AGM 039	3,851,520	1,305,600	18,960	370	65,280	40	16 / 32	12,300	24,600	—

Table 14. M-Series FPGA Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device	CXL* Lane	F-Tile						R-Tile	HPS
		Transceiver Channel				Ethernet Block ²³	PCIe* Controller ²⁴	PCIe* ²⁵/ CXL* ²⁶ Controller
		FGT ²⁷		FHT ²⁸
		32 Gbps NRZ	58 Gbps PAM4	58 Gbps NRZ	116 Gbps PAM4
AGM 032	16²⁹	64	48	8	8	4 ³⁰	4 ³¹	1	Yes
AGM 039	16²⁹	64	48	8	8	4 ³⁰	4 ³¹	1	Yes

Table 15. M-Series FPGA Package with F-TileTable reading example: In package 3184B of AGM 032, there are 720 GPIOs, of which, 360 are LVDS. There are four F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4.
Device	Package (Grid Array: Hexagonal)
	3184B (56 mm × 45 mm) 0.92 mm pitch
	GPIO	LVDS	F-Tile ×4
			FGT		FHT
			32 Gbps NRZ	58 Gbps PAM4	58 Gbps NRZ	116 Gbps PAM4
AGM 032	720	360	64	48	8	8
AGM 039	720	360	64	48	8	8

Table 16. M-Series FPGA Package with F-Tile and HBM2ETable reading example: In package 4700B of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device	Package (Grid Array: Hexagonal)
	4700B (56 mm × 66 mm) 0.92 mm pitch
	GPIO	LVDS	F-Tile ×4				HBM2E (GB)
			FGT		FHT
			32 Gbps NRZ	58 Gbps PAM4	58 Gbps NRZ	116 Gbps PAM4
AGM 032	768	384	64	48	8	8	32
AGM 039	768	384	64	48	8	8	32

Table 17. M-Series FPGA Package with F-Tile, R-Tile, and HBM2ETable reading example: In package 4700A of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device	Package (Grid Array: Hexagonal)
	4700A (56 mm × 66 mm) 0.92 mm pitch
	GPIO	LVDS	F-Tile ×3				R-Tile ×1		HBM2E (GB)
			FGT		FHT		32 Gbps PCIe*	CXL*
			32 Gbps NRZ	58 Gbps PAM4	58 Gbps NRZ	116 Gbps PAM4	32 Gbps PCIe*	CXL*
AGM 032	768	384	48	36	8	8	16	16	16 / 32
AGM 039	768	384	48	36	8	8	16	16	16 / 32

²³ Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.

²⁴ Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).

²⁵ Maximum PCIe* hard IP blocks ( PCIe* 5.0 ×16) or bifurcatable two PCIe* 5.0 ×8 (EP) or four PCIe* 5.0 ×4 (RP).

²⁶ Maximum CXL* hard IP blocks ( PCIe* 5.0 ×16) endpoint.

²⁷ Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.

²⁸ Maximum F-Tile high speed transceiver (FHT) RS and KP FEC NRZ up to 58 Gbps, or PAM4 up to 116 Gbps.

²⁹ Available in package 4700A.

³⁰ Maximum of four F-Tiles in package 3184B.

³¹ Maximum of four PCIe* controllers in package 3184B.