H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 4/09/2024
Public

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Document Table of Contents

B.1.2. ANLT Sequencer Status

Provides the following status bits:
  • Link Ready
  • Auto-negotiation Timeout
  • LT Timeout
  • Sequencer mode for PCS reconfiguration

Offset: 0xB1

Access: RO

ANLT Sequencer Status Fields

Bit Name Description Access Reset
13:8 seq_reconfig_mode Sequencer mode for PCS reconfiguration

6'b000001: AN mode

6'b000010: LT mode (Clause 93)

6'b100000: 100G data mode

All other settings are reserved

  • The sequencer modifies the datapath as required to move through the stages of ANLT
  • This status register lets you know which step is in progress, and how the datapath is configured
RO 0x0
2 seq_lt_timeout Sequencer Link Training Timeout

1: Sequencer had LT Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time LT restarts
RO 0x0
1 seq_an_timeout Sequencer Auto-Negotiation Timeout

1: Sequencer had AN Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time AN restarts
RO 0x0
0 seq_link_ready Sequencer Link Ready

1: The ANLT Sequencer thinks the link is ready for data mode

0: Link not ready

  • This bit is determined by the RX PCS lane alignment status and hi_ber indication, depending on the setting of 0xB0[13] Link Fail if HiBER.
  • If 0xB0[2] Disable Link Fail Inhibit Timer is set, then the sequencer will continue to indicate Link Ready and stay in data mode even if the link status goes down.
RO 0x0