Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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ID 683414
Date 6/25/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9250 Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

1.4. JESD204B IP Core and AD9250 Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9250 module's quick configuration register at address 0x5E. The transceiver data rate, sampling clock frequency, and other JESD204B parameters complies with the AD9250 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6.  Parameter Configuration
Configuration Setting
JESD204B Parameters LMF 112 124 222 211
HD 0 0 0 1
S 1 1 1 1
N 14 14 14 14
N' 16 16 16 16
CS 0 0 0 0
CF 0 0 0 0
FPGA Clock Device Clock (MHz) 3 122.88
Management Clock (MHz) 100
Frame Clock/Sampling Clock (MHz) 4 245.76 122.88 245.76 245.76
Link Clock (MHz) 4 122.88 61.44
/K/ Character Replacement Enabled
Data Pattern

PRBS-9

Ramp 5

3 The device clock is used to clock the transceiver.
4 The frame clock and link clock is derived from the device clock using an internal PLL.
5 The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3 only.
Level Two Title