AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

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ID 683409
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Creating Synthesis-Only Revisions

To create synthesis-only revisions for the personas, you must assign the top-level entity and corresponding SystemVerilog file for each of the personas:
  1. In the Intel® Quartus® Prime software, click Project > Revisions.
  2. Create blinking_led_default revision based on blinking_led revision. Do not set this revision as current revision.
  3. Modify blinking_led_default.qsf file to include the following assignments:
    set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child 
set_global_assignment -name SYSTEMVERILOG_FILE
  4. Similarly, create blinking_led_child_slow, blinking_led_child_empty, blinking_led_parent, and blinking_led_parent_slow revisions based on blinking_led revision. Do not set these revisions as current revision.
  5. Update the blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.qsf files with their corresponding TOP_LEVEL_ENTITY and SYSTEMVERILOG_FILE assignments:
    ##blinking_led_child_slow.qsf
set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child_slow 
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child_slow.sv
    ##blinking_led_child_empty.qsf
set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_child_empty
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child_empty.sv
    ##blinking_led_parent.qsf

set_global_assignment -name TOP_LEVEL_ENTITY blinking_led
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led.sv
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child.sv

    ##blinking_led_parent_slow.qsf

set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_slow
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_slow.sv
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_child.sv
  6. To avoid synthesis errors, ensure that the synthesis revision files for the child partitions do not contain any design partition, pin assignments, or Logic Lock region assignments. Also, the synthesis revision files for the parent partitions must only contain design partition assignments for the corresponding child partitions. Remove these assignments, if any, in the blinking_led_default.qsf, blinking_led_child_slow.qsf, blinking_led_child_empty.qsf, blinking_led_parent.qsf, and blinking_led_parent_slow.qsf files:
    #set_instance_assignment -name PARTITION pr_partition -to \
        u_blinking_led|u_blinking_led_child
#set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
        u_blinking_led|u_blinking_led_child
#set_instance_assignment -name PLACE_REGION "69 10 88 29" -to \
        u_blinking_led|u_blinking_led_child  
#set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
        u_blinking_led|u_blinking_led_child  
#set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
        u_blinking_led|u_blinking_led_child  
#set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to \
        u_blinking_led|u_blinking_led_child
#set_instance_assignment -name PARTITION pr_parent_partition -to \
        u_blinking_led
#set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
        u_blinking_led
#set_instance_assignment -name PLACE_REGION “66 7 112 32” -to \
        u_blinking_led
#set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
        u_blinking_led
#set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
        u_blinking_led
#set_instance_assignment -name ROUTE_REGION “65 6 113 33” -to \
        u_blinking_led
  7. Include the following assignments in blinking_led_parent.qsf and blinking_led_parent_slow.qsf files:
    set_instance_assignment -name PARTITION pr_partition -to \
        u_blinking_led_child 
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to \
        u_blinking_led_child
  8. Verify that the blinking_led.qpf file contains the following revisions, in no particular order:
    PROJECT_REVISION = "blinking_led"
PROJECT_REVISION = "blinking_led_pr_alpha"
PROJECT_REVISION = "blinking_led_pr_bravo"
PROJECT_REVISION = "blinking_led_pr_charlie"
PROJECT_REVISION = “blinking_led_pr_delta”
PROJECT_REVISION = “blinking_led_pr_emma”
PROJECT_REVISION = "blinking_led_default"
PROJECT_REVISION = "blinking_led_child_slow"
PROJECT_REVISION = "blinking_led_child_empty"
PROJECT_REVISION = “blinking_led”
PROJECT_REVISION = “blinking_led_slow”
    Note: If you are copying the revision files from hpr folder, manually update the blinking_led.qpf file with the above lines of code.
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