LDPC IP Core User Guide

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ID 683381
Date 4/04/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 2. LDPC IP EOL 2. About the LDPC IP Core 3. Getting Started with the LDPC IP Core 4. LDPC IP Core Specifications 5. Document Revision History A. LDPC IP Core Document Archive
2. About the LDPC IP Core x
2.1. LDPC IP Core Features 2.2. LDPC IP Device Family Support 2.3. LDPC IP Core Release Information 2.4. DSP Intel® FPGA IP Verification 2.5. LDPC IP Core Performance
3. Getting Started with the LDPC IP Core x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. IP Catalog and Parameter Editor 3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.4. Simulating Intel® FPGA IP Cores
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode 3.1.2. LDPC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
3.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. LDPC IP Core Specifications x
4.1. LDPC IP Core Interfaces 4.2. LDPC IP Core Parameters
4.1. LDPC IP Core Interfaces x
4.1.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.1.2. Clock and Reset Interfaces 4.1.3. LDPC IP Core Signals
4.1.3. LDPC IP Core Signals x
4.1.3.1. LDPC IP Core Backpressure
Product Discontinuance Notification
2. LDPC IP EOL
2. About the LDPC IP Core
3. Getting Started with the LDPC IP Core
4. LDPC IP Core Specifications
5. Document Revision History
A. LDPC IP Core Document Archive

4.2. LDPC IP Core Parameters

Table 12.  General Parameters
Parameter Value Description
Standard

DVB-S2

NASA GSFC-STD-9100

WiMedia 1.5

DOCSIS 3.1

WiFi 802.11n

 Type of LDPC code.
LDPC module Encoder or decoder

NASA GSFC-STD-9100, WiMedia 1.5, DOCSIS 3.1, and Wifi 802.11n only.

Codeword length

Encoder DVB-S2: 16200, 64800

Decoder:

  • WiMedia 1.5: 1200, 1320
  • NASA: 8160, 8176
 Number of bits per codeword.
Coding rate

DVB:S2: 1/4 1/3 2/5 1/2 3/5 2/3 3/4 4/5 5/6 8/9

DOCSIS 3.1: 75% 85% 89%

NASA GSFC-STD-9100: 7/8

WiMedia 1.5: 0.5, 0.625, 0.75, 0.8

 -
Number of bits per input symbol 1 to 30 Encoder only.
Number of LLRs per input symbol 2 to 40 (NASA, DOCSIS, and WiMedia) The number of LLRs you feed in parallel to the decoder
Number of softbits per input LLR 2 to 16 Decoder only. The width of the input LLR. Assume that the number of bits per output symbol is equal the number of LLR per input symbol
Table 13.  Decoder Options
Parameter Value Description
Number of decoding iterations 1 to 100 The maximum number of decoding iterations. A decoding iteration corresponds to the decoding of all the rows of the parity-check matrix. The decoder stops decoding once it finds a valid codeword.
Parallelism 1 to 100 The number of rows processed in parallel during the decoding.
Width of the decoder variables 4 or 16 The width of the input LLR. The decoder can represent the LLR it processes by a much larger number of softbits than the input LLRs.
MSA attenuation factor 1, 0.875, 0.75, 0.625, 0.5, 0.375, 0.25 The design applies a constant attenuation factor to the output of the min-sum algorithm (MSA) processing to ease convergence. This factor is a sum of inverse of power of 2.
Full-streaming architecture No or yes With full streaming architecture, the decoder can accept data while decoding if the level of parallelization is sufficient. NASA only.
Layered decoding No or yes NASA GSFC-STD-9100 decoder only
Output parity check bits No or yes Decoder provides output parity check bits or information bits only.
Level Two Title