AN 826: Hierarchical Partial Reconfiguration Tutorial: for Intel® Stratix® 10 GX FPGA Development Board

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ID 683327
Date 1/05/2021
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 826: Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

Document Revision History for AN 826: Hierarchical Partial Reconfiguration Tutorial for Intel® Stratix® 10 GX FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2021.01.05 20.3
  • Updated Intel® Quartus® Prime software version number in "Reference Design Requirements" topic.
  • Updated figures in "Step 3: Creating a Design Partition" topic.
  • Updated figures and QSF assignments in "Step 4: Allocating Placement and Routing Region for a PR Partition" topic.
  • Updated figures and steps in "Creating Implementation Revisions" topic.
  • Corrected typo in "Step 8: Preparing PR Implementation Revisions for Parent PR Partitions" topic.
  • Corrected typo in "Step 9: Preparing PR Implementation Revisions for Child PR Partitions" topic.
  • Indicated support for all Intel® Stratix® 10 FPGA tiles.
2019.07.15 19.1.0
  • Changed default file export location from output_files to project directory.
  • Described new reserved core partition type and related GUI.
  • Corrected the persona type for hpr_parent_slow_child_slow.qsf in "Creating Revisions."
  • Updated Design Partition Window descriptions and screenshots for column display button and new partition properties.
2018.09.24 18.1.0
  • Updated sections - Step 3: Creating Design Partitions, Step 8: Compiling the Base Revision, Step 8: Preparing the PR Implementation Revisions for Parent PR Partition, and Step 9: Preparing the PR Implementation Revisions for Child PR Partitions with the new PR flow that eliminates the need for manual export of finalized snapshot of the static region.
  • Other minor text edits and image updates.

2018.05.07

18.0.0
  • Compilation flow change
  • Other minor text edits

2017.11.06

17.1.0

Initial release of the document
Level Two Title