Viterbi IP Core User Guide

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ID 683280
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Viterbi IP Core 2. Viterbi IP Core Getting Started 3. Viterbi IP Core Functional Description A. Viterbi IP Core User Guide Document Archives 4. Document Revision History
1. About the Viterbi IP Core x
1.1. Intel® DSP IP Core Features 1.2. Viterbi IP Core Features 1.3. DSP IP Core Device Family Support 1.4. DSP IP Core Verification 1.5. Viterbi IP Core Release Information 1.6. Viterbi IP Core Performance and Resource Utilization
2. Viterbi IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Viterbi IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. Viterbi IP Core Functional Description x
3.1. Decoder 3.2. Convolutional Encoder 3.3. Trellis Coded Modulation 3.4. Viterbi IP Core Parameters 3.5. Viterbi IP Core Interfaces and Signals
3.3. Trellis Coded Modulation x
3.3.1. Half-Rate Convolutional Codes 3.3.2. Trellis Decoder 3.3.3. About Converting Received Signals 3.3.4. Trellis Termination 3.3.5. Trellis Initialization
3.4. Viterbi IP Core Parameters x
3.4.1. Architecture 3.4.2. Code Sets 3.4.3. Viterbi Parameters 3.4.4. Test Data
3.4.1. Architecture x
3.4.1.1. BER Estimator 3.4.1.2. Node Synchronization
3.4.3. Viterbi Parameters x
3.4.3.1. Soft Symbol Input 3.4.3.2. State Metrics 3.4.3.3. Throughput Calculator 3.4.3.4. Latency Calculator
3.4.4. Test Data x
3.4.4.1. External Puncturing
3.5. Viterbi IP Core Interfaces and Signals x
3.5.1. Avalon-ST Interfaces in DSP IP Cores 3.5.2. Global Signals 3.5.3. Avalon-ST Sink Signals 3.5.4. Avalon Source-ST Signals 3.5.5. Configuration Signals 3.5.6. Status Signals 3.5.7. Viterbi IP Core Timing Diagrams
1. About the Viterbi IP Core
2. Viterbi IP Core Getting Started
3. Viterbi IP Core Functional Description
A. Viterbi IP Core User Guide Document Archives
4. Document Revision History

1.6. Viterbi IP Core Performance and Resource Utilization

This typical expected performance uses different architectures and constraint length, L, combinations, and ACS units, A, and the Quartus Prime software. Performance largely depends on constraint length, L.

Hybrid Architecture

The typical expected performance for a hybrid Viterbi IP core uses the Quartus Prime software with the Arria V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices and the following parameters:

  • v = 6 × L
  • softbits = 3
  • N = 2

where:

  • v is the traceback length
  • L is the constraint length
  • N is the number of coded bits
  • A is the number of ACS units
Table 3.  Typical Performance
Parameters Device ALM fMAX (MHz) Memory Registers
L A M10K M20K Primary Secondary
5 1 Arria 10 401 383 -- 3 422 40
5 1 Arria V 323 201 5 -- 390 60
5 1 Cyclone V 324 172 5 -- 390 53
5 1 Stratix V 316 432 -- 5 388 44
7 1 Arria 10 521 370 -- 4 559 50
7 1 Arria V 427 207 6 -- 507 58
7 1 Cyclone V 427 185 6 -- 507 74
7 1 Stratix V 417 438 -- 6 506 51
7 2 Arria 10 622 363 -- 4 670 51
7 2 Arria V 529 215 6 -- 625 71
7 2 Cyclone V 532 180 6 -- 625 74
7 2 Stratix V 502 408 -- 6 625 56
7 4 Arria 10 835 366 -- 4 885 101
7 4 Arria V 744 204 6 -- 856 99
7 4 Cyclone V 746 173 6 -- 856 100
7 4 Stratix V 652 382 -- 6 856 82
9 1 Arria 10 932 343 -- 9 970 88
1 Arria V 792 190 11 -- 927 90
9 1 Cyclone V 794 176 11 -- 926 96
9 1 Stratix V 777 393 -- 11 924 94
9 16 Arria V 2,118 188 17 -- 2,743 309
9 16 Cyclone V 2,119 163 17 -- 2,744 275
9 16 Stratix V 1,887 348 -- 17 2,738 198
9 2 Arria 10 1,029 363 -- 9 1,091 74
9 2 Arria V 889 205 11 -- 1,053 98
9 2 Cyclone V 889 180 11 -- 1,053 96
9 2 Stratix V 883 377 -- 11 1,053 115
9 4 Arria 10 1,240 298 -- 9 1,321 87
9 4 Arria V 1,097 201 11 -- 1,302 137
9 4 Cyclone V 1,096 159 11 -- 1,302 126
9 4 Stratix V 1,021 390 -- 11 1,302 119
9 8 Arria V 1,465 197 13 -- 1,788 193
9 8 Cyclone V 1,465 163 13 -- 1,789 191
9 8 Stratix V 1,398 351 -- 13 1,790 154

Parallel Architecture

The typical expected performance for a parallel Viterbi IP core uses the Quartus Prime software with the Arria V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices. The following parameters apply:

  • v = 6 ×L
  • N = 2

where:

  • v is the traceback length
  • L is the constraint length
  • N is the number of coded bits
Table 4.  Typical Performance
Parameters Device ALMs

fMAX

(MHz)

 Memory Registers
softbits L Optimization Best State Finder M10K M20K Primary Secondary
5 3 — On Arria 10 420 400 -- 5 500 63
7 3 — On Arria 10 453 351 -- 5 534 75
3 3 — Off Arria 10 396 423 -- 5 473 39
5 3 — Off Arria 10 420 400 -- 5 500 63
7 3 — Off Arria 10 453 351 -- 5 534 75
3 7 Block Off Arria 10 1,454 354 -- 3 817 154
3 7 Block Off Arria V 1,537 201 5 -- 1,166 168
3 7 Block Off Cyclone V 1,544 149 5 -- 1,167 88
3 7 Block Off Stratix V 1,521 352 -- 3 1,167 154
3 3 — Off Arria V 378 237 5 -- 456 67
3 3 — Off Cyclone V 378 200 5 -- 456 84
3 3 — Off Stratix V 378 405 -- 5 455 45
5 3 — Off Arria V 397 210 5 -- 483 68
5 3 — Off Cyclone V 397 188 5 -- 484 81
5 3 — Off Stratix V 396 406 -- 5 482 92
3 3 — On Arria V 378 237 5 -- 456 67
3 3 — On Cyclone V 378 200 5 -- 456 84
3 3 — On Stratix V 378 405 -- 5 455 45
5 3 — On Arria V 397 210 5 -- 483 68
5 3 — On Cyclone V 397 188 5 -- 484 81
5 3 — On Stratix V 396 406 -- 5 482 92
7 3 — On Arria V 424 219 5 -- 518 82
7 3 — On Cyclone V 424 185 5 -- 519 76
7 3 — On Stratix V 424 408 -- 5 517 69
7 3 — Off Arria V 424 219 5 -- 518 82
7 3 — Off Cyclone V 424 185 5 -- 519 76
7 3 — Off Stratix V 424 408 -- 5 517 69
7 4 — Off Arria V 424 219 5 -- 518 82
7 4 — Off Cyclone V 424 185 5 -- 519 76
7 4 — Off Stratix V 424 408 -- 5 517 69
3 7 Continuous Off Arria 10 1,180 365 -- 5 829 178
3 7 Continuous Off Arria V 1,222 187 9 -- 1,137 250
3 7 Continuous Off Cyclone V 1,223 157 9 -- 1,137 187
3 7 Continuous Off Stratix V 1,220 325 -- 5 1,137 168
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