AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
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Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Step 9: Preparing the PR Implementation Revisions for Parent PR Partition

You must prepare the parent and child PR implementation revisions before you can generate the PR bitstream for device programming. This setup includes mapping the new PR logic to the preexisting parent PR partition.
  1. To set the current revision, click Project > Revisions, select hpr_parent_slow_child_default as the Revision name, and then click Set Current.
  2. To verify the correct source for each implementation revision, click Project > Add/Remove Files in Project. Confirm that the blinking_led_child.sv file appears in the file list.
    Figure 12. Confirming Correct Source File
  3. To specify the .qdb file associated with the static region, click Assignments > Design Partitions Window. Double-click the Partition Database File cell for root_partition and select the <project_directory>/blinking_led_static.qdb file.
    Figure 13. Assigning the Partition Database File
    Alternatively, the following command assigns this file: 
    set_instance_assignment -name QDB_FILE_PARTITION \
	blinking_led_static.qdb -to |
  4. In the Entity Re-binding cell for pr_parent_partition, specify the entity name the PR parent partition. For this implementation revision, the entity name is blinking_led_slow. blinking_led_slow is the name of the entity that you are partially reconfiguring. u_blinking_led is the name of the instance that your entity overwrites during PR.
  5. Verify that the following line now exists in the .qsf:
    Figure 14. Entity Rebinding 
    #hpr_parent_slow_child_default.qsf
set_instance_assignment -name ENTITY_REBINDING \
      blinking_led_slow -to u_blinking_led
    Note: Because the child PR logic is already defined by the parent PR partition, whose entity name is rebound, do not use an entity rebinding assignment for the child PR partition.
  6. In the Logic Lock Regions window, define the same Logic Lock region for the child PR partition as the parent PR partition.
    Figure 15. Defining Logic Lock Regions
    Note: There is no requirement to redefine the Logic Lock region for the parent PR partition.
  7. Before compiling the implementation revision, ensure the corresponding .qsf file contains the following assignments: 
    set_global_assignment -name GENERATE_PR_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
    These assignments allow the Assembler to automatically generate the required PR bitstreams.
  8. To compile the design, click Processing > Start Compilation. Alternatively, the following command compiles this project: 
    quartus_sh --flow compile blinking_led –c hpr_parent_slow_child_default
  9. To export this new parent PR partition as a finalized .qdb file, click Project > Export Design Partition. Specify the following options for the partition:
    Option Setting
    Partition name pr_parent_partition
    Partition database file <project>/pr_parent_partition_slow_final.qdb
    Include entity-bound SDC files Enable
    Snapshot Final

    Alternatively, the following command exports the parent PR region:

    quartus_cdb -r blinking_led -c blinking led --export_block \ 
      root_partition --snapshot final --file \
      pr_parent_partition_slow_final.qdb
  10. Inspect the bitstream files generated to the output_files directory.
    Table 6.  Generated Bitstream Files
    Name Type Description
    hpr_parent_slow_child_default.pr_parent_partition.rbf PR bitstream file for parent PR partition Used to program the default persona for the parent PR region. Causes the led_two_on to blink at a lower rate.
    hpr_parent_slow_child_default.pr_parent_partition.pr_partition.rbf PR bitstream file for child PR partition Used to program the default persona for the child PR region. Causes the led_three_on to blink at the default rate.
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