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1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
3.1. Memory Block Types
3.2. Write and Read Operations Triggering
3.3. Port Width Configurations
3.4. Mixed-width Port Configuration
3.5. Mixed-width Ratio Configuration
3.6. Maximum Block Depth Configuration
3.7. Clocking Modes and Clock Enable
3.8. Memory Blocks Address Clock Enable Support
3.9. Byte Enable
3.10. Asynchronous Clear
3.11. Read Enable
3.12. Read-During-Write
3.13. Power-Up Conditions and Memory Initialization
3.14. Error Correction Code
3.15. Freeze Logic
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3.10. Asynchronous Clear
The embedded memory blocks in the Arria II GX, Arria II GZ, Stratix IV, Stratix V, and newer device families support the asynchronous clear feature used on the output latches and output registers. Therefore, if your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear. The asynchronous clear feature allows you to clear the outputs even if the q output port is not registered. However, this feature is not supported in MLAB memory blocks.
The outputs stay cleared until the next clock. However, in Arria V, Cyclone V, and Stratix V devices, the outputs stay cleared until the next read.
Note: You cannot use the asynchronous clear port to clear the contents of the embedded memory. Use the asynchronous clear port to clear the contents of the input and output register stages only.
| Memory Mode | Arria II GX, Arria II GZ, Arria V, Cyclone V, Stratix IV, Stratix V, and newer devices |
|---|---|
| Single-port RAM | All registered input ports are not affected. 6 |
| Single dual-port RAM and True dual-port RAM | Only registered input read address port can be affected. |
| Single-port ROM | Registered input address port can be affected. |
| Dual-port ROM | All registered input ports are not affected. |
Note: During a read operation, clearing the input read address asynchronously corrupts the memory contents. The same effect applies to a write operation if the write address is cleared.
Note: Beginning from Arria V, Cyclone V, and Stratix V devices onwards, an output clock signal is needed to successfully recover the output latch from an asynchronous clear signal. This implies that in a single clock mode true dual-port RAM, setting clock enabled on the registered output may affect the recovery of the unregistered output because they share the same output clock signal. To avoid this, provide an output clock signal (with clock enabled) to the output latch to deassert an asynchronous clear signal from the output latch.
6 When LCs are implemented in this memory mode, registered output port is not affected.