O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 1/24/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

4. O-RAN IP Registers

Control and monitor O-RAN IP functionality through control and status interface.
Table 20.  Register Map
CSR_ADDRESS (Word Offset) Register Name
0x0 t2a_min_up
0x1 t2a_max_up
0x2 t2a_min_cp_ul
0x3 t2a_max_cp_ul
0x4 t2a_min_cp_dl
0x5 t2a_max_cp_dl
0x6 ta3_min_up
0x7 ta3_max_up
0x8 rx_window_enable
0x9 tx_window_enable
0xA functional_mode
0xB static_udCompHdr
0xC tx_error
0xD rx_error
0xE tx_error_mask
0xF rx_error_mask
0x10 error_log
0x11 rx_total_low
0x12 rx_total_high
0x13 rx_on_time_low
0x14 rx_on_time_high
0x15 rx early low
0x16 rx_early_high
0x17 rx_late_low
0x18 rx_late_high
0x19 – 0x28 rx_on_time_c_low_uplink {0 .. 15}
0x29 – 0x38 rx_on_time_c_high uplink {0 .. 15}
0x39 – 0x48 rx_early_c_low_uplink {0 .. 15}
0x49 – 0x58 rx_early_c_high_uplink {0 .. 15}
0x59 – 0x68 rx_late_c_low_uplink {0 .. 15}
0x69 – 0x78 rx_late_c_high_uplink {0 .. 15}
0x79 – 0x88 rx_on_time_c_low_downlink {0 .. 15}
0x89 – 0x98 rx_on_time_c_high_downlink {0 .. 15}
0x99 – 0xA8 rx_early_c_low_downlink {0 .. 15}
0xA9 – 0xB8 rx_early_c_high_downlink {0 .. 15}
0xB9 – 0xC8 rx_late_clow_downlink {0 .. 15}
0xC9 – 0xD8 rx_late_c_high_downlink {0 .. 15}
0xD9 tx_total_low
0xDA tx_total_high
0xDB tx_total_c_low
0xDC tx_total_c_high
Table 21.  t2a_min_up Register
Bit Width Description Access HW Reset Value
31:0 Minimum RU to antenna uplink delay in nS. RW 0x0
Table 22.  t2a_max_up Register
Bit Width Description Access HW Reset Value
31:0 Maximum RU to antenna uplink delay in nS. RW 0x0
Table 23.  t2a_min_cp_ul Register
Bit Width Description Access HW Reset Value
31:0 Minimum RU to antenna uplink control plane delay in nS. RW 0x0
Table 24.  t2a_max_cp_ul Register
Bit Width Description Access HW Reset Value
31:0 Maximum RU to antenna uplink control plane delay in nS. RW 0x0
Table 25.  t2a_min_cp_dl Register
Bit Width Description Access HW Reset Value
31:0 Minimum RU to antenna downlink control plane delay in nS. RW 0x0
Table 26.  t2a_max_cp_dl Register
Bit Width Description Access HW Reset Value
31:0 Maximum RU to antenna uplink control plane delay in nS. RW 0x0
Table 27.  ta3_min_up Register
Bit Width Description Access HW Reset Value
31:0 Minimum antenna to RU uplink delay in nS. RW 0x0
Table 28.  ta3_max_up Register
Bit Width Description Access HW Reset Value
31:0 Maximum antenna to RU uplink delay in nS. RW 0x0
Table 29.  rx_window_enable Register
Bit Width Description Access HW Reset Value
31:1 Reserved RO 0x0
0:0 Receiver window enable RW 0x0
Table 30.  tx_window_enable Register
Bit Width Description Access HW Reset Value
31:1 Reserved RO 0x0
0:0 Transmission window enable RW 0x0
Table 31.  functional_mode Register
Bit Width Description Access HW Reset Value
31:2 Reserved RO 0x0
1:1

Performance counter reset

1 – Reset all performance counters

0 – No action

 RW1S 0x0
0:0

Functional mode:

0 – Static compression mode

1 – Dynamic compression mode

 RW 0x0
Table 32.  static_udCompHdr Register
Bit Width Description Access HW Reset Value
31:8 Reserved RO 0x0
7:0

Static user data compression header

7:4 – udIqWidth

4’b0000 – 16 bits

4’b1111 – 15 bits

:

4’b0001 – 1 bit

3:0 - udCompMeth

4’b0000 – No compression

4’b0001 – Block Floating Point

4’b0011 - µ-law

Others - reserved

RW 0x0
Table 33.  tx_error Register
Bit Width Description Access HW Reset Value
31:8 Reserved RO 0x0
7:7 Invalid C-Plane request section type RW1C 0x0
6:6 Section 3 mapper section FIFO overflow RW1C 0x0
5:5 Section 3 mapper common FIFO overflow RW1C 0x0
4:4 Section 1 mapper section FIFO overflow RW1C 0x0
3:3 Section 1 mapper common FIFO overflow RW1C 0x0
2:2 Section 0 mapper section fifo overflow RW1C 0x0
1:1 Section 0 mapper common FIFO overflow RW1C 0x0
0:0 Transmission window check error RW1C 0x0
Table 34.  rx_error Register
Bit Width Description Access HW Reset Value
31:6 Reserved RO 0x0
5:5 Incoming Avalon Streaming error packet RW1C 0x0
4:4 Invalid receiver U-plane request—udCompHdr fields RW1C 0x0
3:3 Invalid receiver U-plane request—PRB fields RW1C 0x0
2:2 Invalid receiver C-plane request—section header RW1C 0x0
1:1 Invalid receiver C-plane request—common header RW1C 0x0
0:0 Reception window check error RW1C 0x0
Table 35.  tx_error_mask Register
Bit Width Description Access HW Reset Value
31:1 Reserved RO 0x0
0:0 Transmission window check error mask RW 0x0
Table 36.  rx_error_mask Register
Bit Width Description Access HW Reset Value
31:6 Reserved RO 0x0
5:5 Incoming Avalon Streaming error packet error mask RW 0x0
4:4 Invalid receiver U-plane request—udCompHdr fields RW 0x0
3:3 Invalid receiver U-plane request—PRB fields error mask RW 0x0
2:2 Invalid receiver C-plane request—section header error mask RW 0x0
1:1 Invalid receiver C-plane request—common header error mask RW 0x0
0:0 Receiver window check error mask RW 0x0
Table 37.  error_log Register
Bit Width Description Access HW Reset Value
31:8 Reserved RO 0x0
7:0 Error C-plane request—section type RO 0x0
Table 38.  rx_total_low Register
Bit Width Description Access HW Reset Value
31:0

Total number of control and user plane eCPRI messages received. Lower 32b of the counter.

RO 0x0
Table 39.  rx_total_high Register
Bit Width Description Access HW Reset Value
31:0

Total number of control and user plane eCPRI messages received. Upper 32b of the counter.

RO 0x0
Table 40.  rx_on_time_low Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane (eCPRI type 0) messages that arrive within the specified time window. Lower 32b of the counter.

RO 0x0
Table 41.  rx_on_time_high Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound user plane (eCPRI type 0) messages that arrive within the specified time window. Upper 32b of the counter. RO 0x0
Table 42.  rx_early_low Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time. Lower 32b of the counter.

RO 0x0
Table 43.  rx_early_high Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time. Upper 32b of the counter.

RO 0x0
Table 44.  rx_late_low Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive after the end of the designated receive window time. Lower 32b of the counter.

RO 0x0
Table 45.  rx_late_high Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive after the end of the designated receive window time. Upper 32b of the counter.

RO 0x0
Table 46.  rx_on_time_c_low_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound control plane (eCPRI type 2) messages that arrive within the specified time window on uplink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 47.  rx_on_time_c_high_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound control plane (eCPRI type 2) messages that arrive within the specified time window on uplink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 48.  rx_early_c_low_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time on uplink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 49.  rx_early_c_high_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time on uplink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 50.  rx_late_c_low_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive after the end of the designated receive window time on uplink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 51.  rx_late_c_high_{0..15}_uplink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound user plane messages that the IP detects to arrive after the end of their designated receive window time on uplink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 52.  rx_on_time_c_low_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound control plane (ecpri type 2) messages that arrive within the specified time window on downlink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 53.  rx_on_time_c_high_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound control plane (eCPRI type 2) messages that arrive within the specified time window on downlink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 54.  rx_early_c_low_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time on downlink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 55.  rx_early_c_high_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound user plane messages that the IP detects to arrive before the start of the designated receive window time on downlink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 56.  rx_late_c_low_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0

The number of inbound user plane messages that the IP detects to arrive after the end of the designated receive window time on downlink. Lower 32b of the counter For DU_PortId = {0..15}.

RO 0x0
Table 57.  rx_late_c_high_{0..15}_downlink Register
Bit Width Description Access HW Reset Value
31:0 The number of inbound user plane messages that the IP detects to arrive after the end of the designated receive window time on downlink. Upper 32b of the counter For DU_PortId = {0..15}. RO 0x0
Table 58.  tx_total_low Register
Bit Width Description Access HW Reset Value
31:0

Total number of control and user plane eCPRI messages sent. Lower 32b of the counter.

RO 0x0
Table 59.  tx_total_high Register
Bit Width Description Access HW Reset Value
31:0

Total number of control and user plane eCPRI messages sent. Upper 32b of the counter.

RO 0x0
Table 60.  tx_total_c_low Register
Bit Width Description Access HW Reset Value
31:0

Total number of control plane eCPRI messages sent. Lower 32b of the counter.

RO 0x0
Table 61.  tx_total_c_high Register
Bit Width Description Access HW Reset Value
31:0

Total number of control plane eCPRI messages sent. Upper 32b of the counter.

RO 0x0
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