Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.10.2. HPS External Memory

A 40-bit HPS DDR3/4 memory interface (32-bit data and 8-bit ECC data) assigned to FPGA 2K and 2J I/O banks is connected to a HILO memory daughtercard.

Table 51.  Bank 2K and 2J I/O Pin Assignments for DDR3 and DDR4 Interface
BANK Pin Number DDR3 Interface DDR4 Interface Schematic Name
2K P25 DM4 DM4 HMEM_DQ_ADDR_CMD0
2K N25 DQ4 bit DQ4 bit HMEM_DQ_ADDR_CMD3
2K L26 DQ4 bit DQ4 bit HMEM_DQ_ADDR_CMD4
2K K26 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD2
2K M25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD1
2K L25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD5
2K L24 DQS4_n DQS4_n HMEM_DQS_ADDR_CMD_N
2K K25 DQS4_p DQS4_P HMEM_DQS_ADDR_CMD_P
2K N24 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD6
2K M24 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD7
2K J25 DQ4 bit DQ bit HMEM_DQ_ADDR_CMD8
2K J26
2K J24 BA2 BG0 HMEM_ADDR_CMD18
2K H24 BA1 BA1 HMEM_ADDR_CMD17
2K E25 BA0 BA0 HMEM_ADDR_CMD16
2K D25 CASn A17 HMEM_ADDR_CMD19
2K F23 RASn A16 HMEM_ADDR_CMD26
2K F24 A15 A15 HMEM_ADDR_CMD15
2K G25 A14 A14 HMEM_ADDR_CMD14
2K G26 A13 A13 HMEM_ADDR_CMD13
2K F26 A12 A12 HMEM_ADDR_CMD12
2K E26 240 ohm reference resistor 240 ohm reference resistor RZQ_2K
2K G24 133Mhz DDR reference clock 133Mhz DDR reference clock CLK_HPSEMI_N
2K F25 133Mhz DDR reference clock 133Mhz DDR reference clock CLK_HPSEMI_P
2K D24 A11 A11 HMEM_ADDR_CMD11
2K C24 A10 A10 HMEM_ADDR_CMD10
2K E23 A9 A9 HMEM_ADDR_CMD9
2K D23 A8 A8 HMEM_ADDR_CMD8
2K C23 A7 A7 HMEM_ADDR_CMD7
2K B22 A6 A6 HMEM_ADDR_CMD6
2K B24 A5 A5 HMEM_ADDR_CMD5
2K C25 A4 A4 HMEM_ADDR_CMD4
2K C21 A3 A3 HMEM_ADDR_CMD3
2K C22 A2 A2 HMEM_ADDR_CMD2
2K C26 A1 A1 HMEM_ADDR_CMD1
2K B26 A0 A0 HMEM_ADDR_CMD0
2K A18 No use PAR HMEM_ADDR_CMD31
2K A17 No use CSN1 HMEM_ADDR_CMD30
2K B19 DDR3 interface clock DDR4 interface clock

HMEM_CLK_N
2K B20 DDR3 interface clock DDR4 interface clock HMEM_CLK_P
2K A23 ClKe1 CKe1 HMEM_ADDR_CMD21
2K A24 CKe0 CKe0 HMEM_ADDR_CMD20
2K A25 ODT1 ODT1 HMEM_ADDR_CMD25
2K A26 ODT0 ODT0 HMEM_ADDR_CMD24
2K B21 CSn1 ACTn HMEM_ADDR_CMD23
2K A22 CSn0 CSn0 HMEM_ADDR_CMD22
2K A19 Resetn Resetn HMEM_ADDR_CMD27
2K A20 Wen BG1 HMEM_ADDR_CMD28
2J AV26 DM3 DM3 HPSMEM_DMA0
2J AV27 DQ3 bit DQ3 bit HMEM_DQA4
2J AU27 DQ3 bit DQ3 bit HMEM_DQA5
2J AU28 DQ3 bit DQ3 bit HMEM_DQA6
2J AV28 DQ3 bit DQ3 bit HMEM_DQA1
2J AW28 DQ3 bit DQ3 bit HMEM_DQA0
2J AW25 DQS 3n DQS_n3 HMEM_DQSA_N0
2J AW26 DQS 3p DQS _p3 HMEM_DQSA_P0
2J AV24 DQ3 bit DQ3 bit HMEM_DQA2
2J AW24 DQ3 bit DQ3 bit HMEM_DQA3
2J AV23 DQ3 bit DQ3 bit HMEM_DQA7
2J AW23
2J AU25 DM2 DM2 HPSMEM_DMA1
2J AU26 DQ2 bit DQ2 bit HMEM_DQA8
2J AR26 DQ2 bit DQ2 bit HMEM_DQA11
2J AT26 DQ2 bit DQ2 bit HMEM_DQA10
2J AT23 DQ2 bit DQ2 bit HMEM_DQA14
2J AU24 DQ2 bit DQ2 bit HMEM_DQA12
2J AT24 DQS2n DQS_n2 HMEM_DQSA_N1
2J AT25 DQS2p DQS_p2 HMEM_DQSA_P1
2J AP25 DQ2 bit DQ2 bit HMEM_DQA13
2J AR25 DQ2 bit DQ2 bit HMEM_DQA9
2J AP23 DQ2 bit DQ2 bit HMEM_DQA15
2J AP24
2J AN26 DM1 DM1 HPSMEM_DMA2
2J AP26 DQ1 bit DQ1 bit HMEM_DQA22
2J AN23 DQ1 bit DQ1 bit HMEM_DQA17
2J AN24 DQ1 bit DQ1 bit HMEM_DQA18
2J AK26 DQ1 bit DQ1 bit HMEM_DQA19
2J AL26 DQ1 bit DQ1 bit HMEM_DQA16
2J AL25 DQSn1 DQS1n HMEM_DQSA_N2
2J AM25 DQSp1 DQSl1p HMEM_DQSA_P2
2J AK23 DQ1 bit DQ1 bit HMEM_DQA20
2J AL23 DQ1 bit DQ1 bit HMEM_DQA21
2J AM24 DQ1 bit DQ1 bit HMEM_DQA23
2J AL24
2J AH25 DM0 DM0 HPSMEM_DMA3
2J AJ26 DQ0 bit DQ0 bit HMEM_DQA31
2J AH23 DQ0 bit DQ0 bit HMEM_DQA30
2J AH24 DQ0 bit DQ0 bit HMEM_DQA27
2J AJ23 DQ0 bit DQ0 bit HMEM_DQA29
2J AJ24 DQ0 bit DQ0 bit HMEM_DQA28
2J AJ25 DQSn0 DQS0n HMEM_DQSA_N3
2J AK25 DQSp0 DQS0p HMEM_DQSA_P3
2J AF25 DQ0 bit DQ0 bit HMEM_DQA25
2J AG25 DQ0 bit DQ0 bit HMEM_DQA26
2J AF24 DQ0 bit DQ0 bit HMEM_DQA24
2J AG24 No use Alertn HMEM_ADDR_CMD29
Level Two Title