ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
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Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device

Use the fast_read signal to instruct the IP core to read data from the EPCS/EPCQ/EPCQ-L/EPCQ-A device. The ASMI Parallel Intel® FPGA IP core supports two types of fast read data operation: multiple-byte and single-byte operation.
Figure 9. Fast Reading Multiple-ByteThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing multiple-byte fast read command. The latency shown does not correctly indicate the true processing time. The latency only shows the command.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


Figure 10. Fast Reading a Single-ByteThis figure shows an example of single-byte read command. The latency shown does not correctly indicate the true processing time. The latency only shows the command.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


The fast read command is the same as the read command, with the following exceptions:

  • The fast read command produces the first byte of data on the dataout[7..0] port eight cycles later than it appears for the read command.
  • The fast read command is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices, except for EPCS1 and EPCS4 devices.
  • The fast read command can run up to 25 MHz clock frequency.
  • The fast read and the read commands are mutually exclusive—you can use only one of them in each IP core instantiation.
  • The fast read and read operations are mutually exclusive. You can only do either read or fast read operation at a time. The fast read operation is a replacement for the read operation at higher than 20 MHz clock frequency.

The IP core registers the fast_read signal on the rising edge of the clkin signal. For the IP core to register the read command, ensure that the memory address appears on the addr[23..0] signal before the fast_read signal is asserted. The rden signal must also be asserted to enable the fast read command.

After the IP core registers the fast_read signal, the busy signal is asserted to indicate that the fast read command is in progress. The data appears on the dataout[7..0] signal. The first valid byte of fast read data appears eight clock cycles later than it appears in a normal read command. Also, after the first byte, subsequent bytes appear sequentially, similar to any multiple-byte normal read operation. Therefore, the fast read operation performs faster than the read operation. The IP core asserts the data_valid signal for one clock cycle, to indicate dataout[7..0] contains a new valid data.

If you enable the read_address[23..0] signal in the IP parameter editor, the read address for each data byte on dataout[7..0] signal appears on the read_address[23..0] signal.

Assert the rden signal until you have finished reading sequential data from the EPCS/EPCQ/EPCQ-L/EPCQ-A device. This condition allows you to read every memory address from the EPCS/EPCQ/EPCQ-L/EPCQ-A device with a single read command.

The data from the next address appears on the dataout[7..0] signal and its memory address appears on the read_address[23..0] signal at every eight clkin clock cycles. The data_valid signal is asserted for one clock cycle after the new data byte appears on the dataout[7..0] signal. Use the data_valid signal as an indication to capture the new data byte.

When the second-to-last byte of data to be read appears on the dataout[7..0] signal, and the data_valid is asserted, deassert the rden signal to indicate the end of the fast read command. The final data byte appears on the dataout[7..0] signal, the data_valid is reasserted, and then the IP core deasserts the busy signal.

For a single-byte fast read operation, assert the rden and the fast_read signals for a single clock cycle, or deassert the rden at any time before the first data byte appears on the dataout[7..0] signal, and the data_valid signal is asserted for the first time.

Monitor the data_valid signal to ensure you sample the dataout[7..0] signal only when the data_valid signal is asserted.

After the fast read operation is complete, the dataout[7..0] signal holds the value of the last byte read until you issue a new fast read command or reset the device.

Note: The fast_read, rden, and addr[7..0] signals must adhere to setup and hold time requirements for the clkin signal. These signals must remain stable at the rising edge of the clkin signal.
Note: For EPCQ256/EPCQ_L256 or larger devices, the width of the addr and read_address signals is 32 bit.
Note: You must enable the read_dummyclk when using fast read option.

Section Content
EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction
EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction

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