V-Series Transceiver PHY IP Core User Guide

ID 683171
Date 7/26/2022
Public
Document Table of Contents

13.8. SDC Timing Constraints of Stratix V Native PHY

This section describes SDC examples and approaches to identify false timing paths.

The Intel® Quartus® Prime software reports timing violations for asynchronous inputs to the Standard PCS and 10G PCS. Because many violations are for asynchronous paths, they do not represent actual timing failures. You may choose one of the following three approaches to identify these false timing paths to the Intel® Quartus® Prime or TimeQuest software.

In all of these examples, you must substitute you actual signal names for the signal names shown.

Using the set_false_path Constraint to Identify Asynchronous Inputs

You can cut these paths in your Synopsys Design Constraints (.sdc) file by using the set_false_path command as shown in following example.

set_false_path -through {*10gtxbursten*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]

set_false_path -through {*10gtxdiagstatus*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]

set_false_path -through {*10gtxwordslip*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]

set_false_path -through {*10gtxbitslip*} -to [get_registers *10g_tx_pcs*SYNC_DATA_REG*]

set_false_path -through {*10grxbitslip*} -to [get_registers *10g_rx_pcs*SYNC_DATA_REG*]

set_false_path -through {*10grxclrbercount*} -to [get_registers *10g_rx_pcs*SYNC_DATA_REG*] 

set_false_path -through {*10grxclrerrblkcnt*} -to [get_registers *10g_rx_pcs*SYNC_DATA_REG*] 
set_false_path -through {*10grxprbserrclr*} -to [get_registers *10g_rx_pcs*SYNC_DATA_REG*]

set_false_path -through {*8gbitslip*} -to  [get_registers *8g_rx_pcs*SYNC_DATA_REG*]
set_false_path -through {*8gbytordpld*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] 
set_false_path -through {*8gcmpfifoburst*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] 
set_false_path -through {*8gphfifoburstrx*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] 

set_false_path -through {*8gsyncsmen*} -to [get_registers *8g*pcs*SYNC_DATA_REG*]
set_false_path -through {*8gwrdisablerx*} -to [get_registers *8g_rx_pcs*SYNC_DATA_REG*] 
set_false_path -through {*rxpolarity*} -to [get_registers *SYNC_DATA_REG*]
set_false_path -through {*pldeidleinfersel*} -to [get_registers *SYNC_DATA_REG*]

Using the max_delay Constraint to Identify Asynchronous Inputs

You can use the set_max_delay constraint on a given path to create a constraint for asynchronous signals that do not have a specific clock relationship but require a maximum path delay. The following example illustrates this approach.

# Example: Apply 10ns max delay

set_max_delay -from *tx_from_fifo* -to *8g*pcs*SYNC_DATA_REG1 10

Using the set_false TimeQuest Constraint to Identify Asynchronous Inputs

You can use the set_false path command only during Timequest timing analysis. The following example illustrates this approach.

#if {$::TimeQuestInfo(nameofexecutable) eq "quartus_fit"} {
 
#} else {

#set_false_path -from [get_registers {*tx_from_fifo*}] -through {*txbursten*} -to [get_registers *8g_*_pcs*SYNC_DATA_REG