You can program, erase, and verify the UFM block through the JTAG port or through connections to and from the logic array in accordance with the following IEEE standards:

• IEEE Std. 1532-2002 for MAX II and MAX V devices
• IEEE Std. 1149.1 for MAX 10 devices

There are 13 interface signals to and from the UFM block and the logic array that allow the logic array to read from or write to the UFM during device user mode for MAX II and MAX V devices only.

For MAX II and MAX V devices, the Altera User Flash Memory for I²C Interface Protocol, Altera User Flash Memory for SPI Interface Protocol, Altera User Flash Memory for Parallel Interface Protocol and ALTUFM_NONE IP cores provide interface logic for a subset of these interfaces. For interfaces not provided by the IP core or design examples, you must create user logic to bridge the UFM block to your desired interface protocol.

The Altera On-Chip Flash IP core provides Avalon-MM interface. Use the SPI or I²C interface protocol to avalon MM interface logic to communicate with the UFM.