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1.1. Intel® Stratix® 10 MX Devices
1.2. Innovations in Intel® Stratix® 10 MX Devices
1.3. Intel® Stratix® 10 MX Features Summary
1.4. Intel® Stratix® 10 MX Block Diagram
1.5. Intel® Stratix® 10 MX Family Plan
1.6. Heterogeneous 3D Stacked HBM2 DRAM Memory
1.7. Intel® Hyperflex™ Core Architecture
1.8. Heterogeneous 3D SiP Transceiver Tiles
1.9. Intel® Stratix® 10 MX Transceivers
1.10. PCI Express Gen1/Gen2/Gen3 Hard IP
1.11. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP
1.12. 10G Ethernet Hard IP
1.13. Interlaken PCS Hard IP
1.14. External Memory and General Purpose I/O
1.15. Adaptive Logic Module (ALM)
1.16. Core Clocking
1.17. Fractional Synthesis PLLs and I/O PLLs
1.18. Internal Embedded Memory
1.19. Variable Precision DSP Block
1.20. Power Management
1.21. Device Configuration and Secure Device Manager (SDM)
1.22. Device Security
1.23. Configuration via Protocol Using PCI Express*
1.24. Partial and Dynamic Reconfiguration
1.25. Fast Forward Compile
1.26. Single Event Upset (SEU) Error Detection and Correction
1.27. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview
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1.23. Configuration via Protocol Using PCI Express*
Configuration via protocol using PCI Express* allows the FPGA to be configured across the PCI Express* bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI Express* hard IP operating in autonomous mode before the FPGA is configured, this technique allows the PCI Express* bus to be powered up and active within the 100 ms time allowed by the PCI Express* specification. Intel® Stratix® 10 MX devices also support partial reconfiguration across the PCI Express* bus which reduces system down time by keeping the PCI Express* link active while the device is being reconfigured.