Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

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ID 683137
Date 11/09/2020
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines
Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines x
Intel® Cyclone® 10 LP Pin Connection Guidelines Power Supply Sharing Guidelines Document Revision History for the Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines
Intel® Cyclone® 10 LP Pin Connection Guidelines x
Clock and PLL Pins Configuration/JTAG Pins Differential I/O Pins Reference Pins Supply Pins Notes to Intel® Cyclone® 10 LP Pin Connection Guidelines
Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

Document Revision History for the Intel® Cyclone® 10 LP Device Family Pin Connection Guidelines

Document Version Changes
2020.11.09 Added DPCLK[0.11] and CDPCLK[0..7] pins in the Clock and PLL Pins table.
2019.11.06 Updated note 2 in the Example Power Supply Sharing Guidelines for Intel® Cyclone® 10 LP Devices figure.
2019.07.03 Updated the connection guidelines of the TMS and TDI pins.
Date Version Description of Changes
November 2017 2017.11.06
  • The document is no longer preliminary.
  • Updated the note reference for the VCCINT and VCCD_PLL[1..4] pins.
  • Updated the note reference for the TDI pin.
June 2017 2017.06.02 Updated the supported configuration schemes.
February 2017 2017.02.13 Initial release.
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