Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

18.1. Core Overview

The EPCS/EPCQA serial flash controller core with Avalon® interface allows Nios® II systems to access an Intel EPCS/EPCQA serial configuration device. Intel provides drivers that integrate into the Nios II hardware abstraction layer (HAL) system library, allowing you to read and write the EPCS/EPCQA device using the familiar HAL application program interface (API) for flash devices.
Note: The EPCS/EPCQA Serial Flash Controller Core does not support Nios® V processor booting from QSPI flash.

Using the EPCS/EPCQA serial flash controller core, Nios® II systems can:

  • Store program code in the EPCS/EPCQA device. The EPCS/EPCQA serial flash controller core provides a boot-loader feature that allows Nios® II systems to store the main program code in an EPCS/EPCQA device.
  • Store non-volatile program data, such as a serial number, a NIC number, and other persistent data.
  • Manage the device configuration data. For example, a network-enabled embedded system can receive new FPGA configuration data over a network, and use the core to program the new data into an EPCS/EPCQA serial configuration device.
    The EPCS/EPCQA serial flash controller core is Platform Designer-ready and integrates easily into any Platform Designer-generated system. The flash programmer utility in the Nios® II IDE allows you to manage and program data contents into the EPCS/EPCQA device.
    Note: Intel is offering an alternative device for EPCS. Refer to Product Discontinuance Notification PDN1708 for more details. For information about migration, refer to AN822: Intel Configuration Device Migration Guideline.

    For information about the EPCS/EPCQA serial configuration device family, refer to the Serial Configuration Devices Data Sheet.

    For details about using the Nios® II HAL API to read and write flash memory, refer to the Nios® II Software Developer's Handbook.

    For details about managing and programming the EPCS/EPCQA memory contents, refer to the Nios® II Flash Programmer User Guide.

    For Nios® II processor users, the EPCS/EPCQA serial flash controller core supersedes the Active Serial Memory Interface (ASMI) device. New designs should use the EPCS/EPCQA serial flash controller core instead of the ASMI core.