AN 802: Intel® Stratix® 10 SoC Device Design Guidelines

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ID 683117
Date 12/14/2020
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines 2. Board Design Guidelines for Stratix 10 SoC FPGAs 3. Interfacing to the FPGA for Stratix 10 SoC FPGAs 4. System Considerations for Stratix 10 SoC FPGAs 5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs 6. Recommended Resources for Stratix 10 SoC FPGAs
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines x
1.1. Introduction to the Stratix 10 SoC Device Design Guidelines Revision History
2. Board Design Guidelines for Stratix 10 SoC FPGAs x
2.1. Pin Connection Considerations for Board Design 2.2. HPS Clocking and Reset Design Considerations 2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory 2.4. Design Guidelines for HPS Interfaces 2.5. HPS EMIF Design Considerations 2.6. HPS Memory Debug 2.7. Boundary Scan for HPS 2.8. Embedded Software Debugging and Trace 2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
2.1. Pin Connection Considerations for Board Design x
2.1.1. Board-Related Intel® Quartus® Prime Settings
2.1.1. Board-Related Intel® Quartus® Prime Settings x
2.1.1.1. Unused Pins
2.2. HPS Clocking and Reset Design Considerations x
2.2.1. HPS Clock Planning 2.2.2. Early Pin Planning and I/O Assignment Analysis 2.2.3. Pin Features and Connections for HPS Clocks, Reset and PoR 2.2.4. Direct to Factory Pin Support for Remote System Update (RSU) Feature 2.2.5. Internal Clocks 2.2.6. HPS Peripheral Reset Management
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory x
2.3.1. HPS Pin Multiplexing Design Considerations 2.3.2. HPS I/O Settings: Constraints and Drive Strengths
2.4. Design Guidelines for HPS Interfaces x
2.4.1. HPS EMAC PHY Interfaces 2.4.2. USB Interface Design Guidelines 2.4.3. SD/MMC and eMMC Card Interface Design Guidelines 2.4.4. Design Guidelines for Flash Interfaces 2.4.5. UART Interface Design Guidelines 2.4.6. I2C Interface Design Guidelines
2.4.1. HPS EMAC PHY Interfaces x
2.4.1.1. PHY Interfaces 2.4.1.2. PHY Interfaces Connected Through FPGA I/O 2.4.1.3. MDIO 2.4.1.4. Common PHY Interface Design Considerations
2.4.1.1. PHY Interfaces x
2.4.1.1.1. RMII 2.4.1.1.2. RGMII
2.4.1.2. PHY Interfaces Connected Through FPGA I/O x
2.4.1.2.1. GMII/MII 2.4.1.2.2. Adapting to RGMII 2.4.1.2.3. Adapting to RMII 2.4.1.2.4. Adapting to SGMII
2.4.1.4. Common PHY Interface Design Considerations x
2.4.1.4.1. Signal Integrity
2.4.4. Design Guidelines for Flash Interfaces x
2.4.4.1. NAND Flash Interface Design Guidelines
2.5. HPS EMIF Design Considerations x
2.5.1. Considerations for Connecting HPS to SDRAM Instantiating the Intel® Stratix® 10 HPS EMIF IP GUIDELINE: Instantiate the Intel® Stratix® 10 External Memory Interfaces for HPS IP in Platform Designer. GUIDELINE: Connect the hps_emif conduit to the HPS component GUIDELINE: You must provide a free running and stable reference clock source to external memory interface before the start of device configuration. GUIDELINE: Make sure the HPS EMIF IP block is not reset while the HPS is accessing external SDRAM or resources in the L3 SDRAM Interconnect. GUIDELINE: Ensure that the HPS memory controller Data Mask (DM) pins are enabled. GUIDELINE: Ensure that you choose only DDR3 or DDR4 components or modules in configurations that are supported by the Stratix 10 EMIF for HPS IP and your specific device and package combination. 2.5.2. HPS SDRAM I/O Locations
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs x
3.1. Overview of HPS Memory-Mapped Interfaces 3.2. Recommended System Topologies 3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs 3.4. Timing Closure for FPGA Accelerators 3.5. Information on How to Configure and Use the Bridges 3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces x
3.1.1. HPS-to-FPGA Bridge 3.1.2. Lightweight HPS-to-FPGA Bridge 3.1.3. FPGA-to-HPS Bridge 3.1.4. FPGA-to-SDRAM Ports 3.1.5. Interface Bandwidths
3.2. Recommended System Topologies x
3.2.1. HPS Accesses to FPGA Fabric 3.2.2. MPU Sharing Data with FPGA 3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA
3.2.3. Examples of Cacheable and Non-Cacheable Data Accesses From the FPGA x
3.2.3.1. Example 1: FPGA Reading Data from HPS SDRAM Directly 3.2.3.2. Example 2: FPGA Writing Data into HPS SDRAM Directly 3.2.3.3. Example 3: FPGA Reading Cache Coherent Data from HPS 3.2.3.4. Example 4: FPGA Writing Cache Coherent Data to HPS
4. System Considerations for Stratix 10 SoC FPGAs x
4.1. Timing Considerations 4.2. Maximizing Performance 4.3. System Level Cache Coherency 4.4. System Considerations for Stratix 10 SoC FPGAs Revision History
4.1. Timing Considerations x
4.1.1. Timing Closure for FPGA Accelerators 4.1.2. USB Interface Design Guidelines
4.1.1. Timing Closure for FPGA Accelerators x
4.1.1.1. HPS First and FPGA First Boot Considerations
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs x
5.1. Overview 5.2. Assembling the Components of Your Software Development Platform 5.3. Golden Hardware Reference Design (GHRD) 5.4. Selecting an Operating System for Your Application 5.5. Assembling Your Software Development Platform for Linux* 5.6. Assembling your Software Development Platform for a Bare-Metal Application 5.7. Assembling your Software Development Platform for Partner OS or RTOS 5.8. Choosing the Bootloader Software 5.9. Selecting Software Tools for Development, Debug and Trace 5.10. Boot And Configuration Considerations 5.11. System Reset Considerations 5.12. Flash Considerations 5.13. Embedded Software Debugging and Trace 5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
5.4. Selecting an Operating System for Your Application x
5.4.1. Using Linux* or RTOS 5.4.2. Developing a Bare-Metal Application 5.4.3. Using the Bootloader as a Bare-Metal Framework 5.4.4. Using Symmetrical vs. Asymmetrical Multiprocessing (SMP vs. AMP) Modes
5.5. Assembling Your Software Development Platform for Linux* x
5.5.1. Golden System Reference Design (GSRD) for Linux* 5.5.2. Source Code Management Considerations
5.9. Selecting Software Tools for Development, Debug and Trace x
5.9.1. Selecting Software Build Tools 5.9.2. Selecting Software Debug Tools 5.9.3. Selecting Software Trace Tools
5.10. Boot And Configuration Considerations x
5.10.1. Configuration Sources 5.10.2. Configuration Flash 5.10.3. Configuration Clock 5.10.4. Selecting HPS Boot Options 5.10.5. HPS Boot Sources 5.10.6. Remote System Update (RSU)
5.12. Flash Considerations x
5.12.1. Flash Programming Method 5.12.2. Using a Single flash for Both FPGA Configuration and HPS Mass Storage
6. Recommended Resources for Stratix 10 SoC FPGAs x
6.1. Device Documentation 6.2. Tools and Software Web Pages 6.3. Recommended Resources for Intel® Stratix® 10 SoC FPGAs Revision History
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs

2.5.1. Considerations for Connecting HPS to SDRAM

The hard memory controller for the Intel® Stratix® 10 HPS is in the FPGA I/O columns along with the other hardware memory controllers. The HPS can use only one hard memory controller, and it is located closest to the HPS block in I/O bank 2M, where the address/command and ECC signals reside. Use I/O Bank 2N for 16-bit and 32-bit interface DQ/DQS data group signals. I/O Bank 2L is used for 64-bit interface DQ/DQS data group signals.

Instantiating the Intel® Stratix® 10 HPS EMIF IP

Connecting external SDRAM to the Intel® Stratix® 10 HPS requires the use of an EMIF IP that is specific to the HPS. Follow the below guidelines for properly instantiating and configuring the correct EMIF IP for the HPS.

GUIDELINE: Instantiate the Intel® Stratix® 10 External Memory Interfaces for HPS IP in Platform Designer.

You must use a specific EMIF IP in Platform Designer to connect the HPS to external SDRAM memory.

The EMIF module is found in the IP catalog pane by selecting: Library > Processors and Peripherals > Hard Processor Components > External Memory Interfaces for HPS Intel® Stratix® 10 .

GUIDELINE: Connect the hps_emif conduit to the HPS component

To connect the HPS to the EMIF in Platform Designer, you must connect the hps_emif conduit in the instantiated emif_s10_hps_0 module to the hps_emif conduit in the stratix10_hps_0 module.

GUIDELINE: You must provide a free running and stable reference clock source to external memory interface before the start of device configuration.

For more information, refer to the Intel® Stratix® 10 External Memory Interfaces IP User Guide.

GUIDELINE: Make sure the HPS EMIF IP block is not reset while the HPS is accessing external SDRAM or resources in the L3 SDRAM Interconnect.

Asserting reset to the HPS EMIF IP block should coincide with the HPS reset assertion unless the application can save and recover context in co-ordination with HPS EMIF IP reset assertion. This can be achieved simply by connecting the HPS EMIF reset input to one or a combination of resets from the following sources: HPS reset outputs (for example: h2f_reset, h2f_cold_reset), other resets in the system that also source an HPS cold reset input (for example: nCONFIG and HPS_COLD_nRESET reset input pin).

If the HPS EMIF IP is reset without resetting the HPS as described above, the application must put the L3 SDRAM Interconnect in reset using the brgmodrst register, bit 6 (ddrsch) in the Reset Manager before HPS EMIF IP reset assertion and not release it until after the HPS EMIF IOPLL has locked. Failure to do so can result in locking up the processor on subsequent accesses to external SDRAM or resources in the L3 SDRAM Interconnect.

GUIDELINE: Ensure that the HPS memory controller Data Mask (DM) pins are enabled.

When you instantiate the memory controller in Platform Designer, you must select the checkbox to enable the data mask pins. If this control is not enabled, data corruption occurs any time a master accesses data in SDRAM that is smaller than the native word size of the memory.
Note: The checkbox to enable data masking is found in the "Parameters" tab for the External Memory Interfaces for HPS Intel® Stratix® 10 Intel® FPGA IP within the Topology section of the memory sub-tab.

GUIDELINE: Ensure that you choose only DDR3 or DDR4 components or modules in configurations that are supported by the Stratix 10 EMIF for HPS IP and your specific device and package combination.

Intel's External Memory Interface Spec Estimator is a parametric tool that allows you to compare supported external memory interface types, configurations and maximum performance characteristics in Intel FPGA and SoC devices.

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