AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents
Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface

MIPI D-PHY IP incorporated in the FPGA is able to receive and transmit serial data which consists of one clock and one or more data lanes. The data lanes can switch between the high-speed and low-power signaling through a passive resistor network in unidirectional mode as shown in the following figures. This may be a spate IP block or integrated into the MIPI CSI-2 protocol controllers depending on the IP source or third-party IP partner. The lane control and interface logic are essential to the D-PHY functionality that needs to be built inside the FPGA logic.

Figure 1. FPGA Unidirectional Receiver Implementation Block DiagramThis figure shows high-speed and low-power modes in a single lane and common resistor configuration.
Figure 2. FPGA Unidirectional Transmitter Implementation Block Diagram

This figure shows high-speed and low-power modes in a single lane and common resistor configuration.

When the interface is in high-speed mode, the MIPI D-PHY RX device presents a 100 Ω differential termination. When the common-mode of the lines indicates that the interface is in low-power mode, the 100 Ω termination is switched to high Z.

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