AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683079
Date 7/15/2019
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Document Table of Contents x
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Incremental Block-Based Compilation Tutorial Revision History
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board

1.3.7. Step 7: Verify Preservation and Optimized Results

After compilation is complete, follow these steps to verify that the Compiler uses the preserved partitions, and that the optimized design block now meets timing requirements:
  1. In the Compilation Report (Processing > Compilation Report), under the Fitter folder, expand the Preserved Assignments folder. The reports indicate use of the preserved partitions.
    Figure 13. Preserved Partitions Report
  2. Click Tools > Timing Analyzer , and then double-click Update Timing Netlist.
  3. Run the report_timing.tcl script to regenerate the timing analysis reports: 
    source report_timing.tcl
    Timing analysis data in the inst_i3 and inst_i4 report folders now indicate that the blinking_led_i3 and blinking_led_i4 partitions meets timing requirements.
    Figure 14. Optimized u_blinking_led_i3 and u_blinking_led_i4 Meet Timing
  4. In the Timing Analyzer reports , right-click the Slow 900 mV 100C Model report in each folder, and then click Generate in All Corners.
  5. Open the Multi Corner Summary report to check the slack and placement results for the big_partition1_top partition. The slack value is similar to performance at the time of preservation. The placement results are the same as at the time of preservation. You can compare these preserved results with Figure 11.
    Figure 15. Preserved Slack and Placement
  6. Repeat step 4 to verify the slack and placement results for the blinking_led_i1 and blinking_led_i2 partitions.
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